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1. 发明授权

US06423623B1 Low Resistance package for semiconductor devices 有权
标题翻译：半导体器件的低电阻封装
公开(公告)号：US06423623B1
公开(公告)日：2002-07-23
申请号：US09141184
申请日：1998-08-27
申请人： Izak Bencuya , Maria Christina B. Estacio , Steven P. Sapp , Consuelo N. Tangpuz , Gilmore S. Baje , Rey D. Maligro
发明人： Izak Bencuya , Maria Christina B. Estacio , Steven P. Sapp , Consuelo N. Tangpuz , Gilmore S. Baje , Rey D. Maligro
IPC分类号： H01L2144
CPC分类号： H01L24/06 , H01L23/49562 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/0603 , H01L2224/16245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48253 , H01L2224/48599 , H01L2224/48699 , H01L2224/49111 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01079 , H01L2924/014 , H01L2924/10161 , H01L2924/10253 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A packaging technique that significantly reduces package resistance. According to the invention, lead frames external to the package are brought in direct contact to solder balls on the surface of the silicon die inside the package molding, eliminating resistive wire interconnections. The packaging technique of the present invention is particularly suitable for power transistors.
摘要翻译：一种显着降低封装电阻的封装技术。根据本发明，封装外部的引线框架与封装模制件内的硅芯片表面上的焊球直接接触，消除了电阻线互连。本发明的封装技术特别适用于功率晶体管。

2. 发明授权

US5879994A Self-aligned method of fabricating terrace gate DMOS transistor 失效
标题翻译：制造平台门DMOS晶体管的自对准方法
公开(公告)号：US5879994A
公开(公告)日：1999-03-09
申请号：US842661
申请日：1997-04-15
申请人： Sze-Hon Kwan , Izak Bencuya , Steven P. Sapp
发明人： Sze-Hon Kwan , Izak Bencuya , Steven P. Sapp
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66712 , H01L21/28114 , H01L29/42368 , H01L29/7802 , Y10S148/126 , Y10S438/975
摘要： An active mask is used to etch field oxide in active areas down to an n- epitaxial substrate. After gate oxide growth, a polysilicon layer is deposited and planarized. The active mask defines the polysilicon gate critical dimension for a terrace gate DMOS structure. The edges of the polysilicon gates are self-aligned to the edges of the thick terrace gate oxide. Because no interlayer alignment is required to delineate the polysilicon gate, the design need not provide for alignment tolerance. A non-critical mask is deposited overlapping the terrace oxide. An etch back to field oxide in exposed areas is performed. An oxide-selective etch is performed to reduce the oxide thickness in source regions. Self-aligned body implantation, body contact masking and implantation, and source masking and implantation are performed. A dielectric is deposited. A source contact mask is deposited and a contact etch is performed. Source metal is deposited, and passivation layer is formed. Gate-drain capacitance caused by polysilicon gate overlap of the substrate is minimized as the overlap is minimized. Because input capacitance is reduced, switching speed is increased. This self-aligned feature also results in a smaller cell pitch dimension and higher packing density. Therefore, the specific ON resistance is reduced and current driving capacity is also greatly elevated.
摘要翻译：使用有源掩模来蚀刻到n-外延衬底的有源区域中的场氧化物。栅极氧化物生长后，沉积多晶硅层并进行平面化。有源掩模定义了用于露台门DMOS结构的多晶硅栅极临界尺寸。多晶硅栅极的边缘与厚平台栅极氧化物的边缘自对准。由于不需要层间对准来描绘多晶硅栅极，所以设计不需要提供对准公差。沉积与阳极氧化物重叠的非关键掩模。执行在暴露区域中回到场氧化物的蚀刻。进行氧化物选择性蚀刻以减少源极区域中的氧化物厚度。进行自对准体植入，体接触掩蔽和植入，以及源掩蔽和植入。沉积电介质。沉积源极接触掩膜并进行接触蚀刻。源金属被沉积，形成钝化层。当重叠被最小化时，由衬底的多晶硅栅极重叠引起的栅 - 漏电容最小化。由于输入电容降低，开关速度提高。这种自对准特征还导致更小的电池间距尺寸和更高的包装密度。因此，特定的导通电阻降低，电流驱动能力也大大提高。

3. 发明授权

US09537258B2 Self unplugging power connector with load current sensing 有权
标题翻译：自负电流检测电源插头
公开(公告)号：US09537258B2
公开(公告)日：2017-01-03
申请号：US14494563
申请日：2014-09-23
申请人： Izak Bencuya
发明人： Izak Bencuya
IPC分类号： H02J7/02 , H01R13/633 , H01R13/66
CPC分类号： H01R13/633 , H01R13/6633 , H01R13/6683
摘要： A self unplugging power connector for charging mobile devices is provided. The self unplugging power connector includes electrical contact members for an electrical outlet, a release mechanism to remove the electrical contact members from the outlet and a current sensing circuit to activate the release mechanism when the circuit senses a current reduction.
摘要翻译：提供一种用于为移动设备充电的自拔电源连接器。自拔式电源连接器包括用于电源插座的电接触构件，用于将电接触构件从出口移除的释放机构以及当电路感测电流减小时激活释放机构的电流感测电路。

4. 发明申请

US20090134458A1 Method of Manufacturing a Trench Transistor Having a Heavy Body Region 有权
标题翻译：具有重体区域的沟槽晶体管的制造方法
公开(公告)号：US20090134458A1
公开(公告)日：2009-05-28
申请号：US12329509
申请日：2008-12-05
申请人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
发明人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
IPC分类号： H01L29/10
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7811
摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.
摘要翻译：提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂很好地围着沉重的身体下面的沉重的身体。

5. 发明授权

US06828195B2 Method of manufacturing a trench transistor having a heavy body region 有权
标题翻译：制造具有重体区域的沟槽晶体管的方法
公开(公告)号：US06828195B2
公开(公告)日：2004-12-07
申请号：US10347254
申请日：2003-01-17
申请人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
发明人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7811
摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.
摘要翻译：提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂很好地围着沉重的身体下面的沉重的身体。

6. 发明授权

US06696726B1 Vertical MOSFET with ultra-low resistance and low gate charge 有权
标题翻译：具有超低电阻和低栅极电荷的垂直MOSFET
公开(公告)号：US06696726B1
公开(公告)日：2004-02-24
申请号：US09640955
申请日：2000-08-16
申请人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
发明人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/42368
摘要： A vertical trench double-diffused metal-oxide-semiconductor (DMOS) field effect transistor characterized by a reduced drain-to-source resistance and a lower gate charge and providing a high transconductance and an enhanced frequency response.
摘要翻译：垂直沟槽双扩散金属氧化物半导体（DMOS）场效应晶体管，其特征在于降低的漏极 - 源极电阻和较低的栅极电荷，并提供高跨导和增强的频率响应。

7. 发明授权

US06429481B1 Field effect transistor and method of its manufacture 失效
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US06429481B1
公开(公告)日：2002-08-06
申请号：US08970221
申请日：1997-11-14
申请人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
发明人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
IPC分类号： H01L2978
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7811
摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.
摘要翻译：提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂很好地围着沉重的身体下面的沉重的身体。

8. 发明授权

US5136349A Closed cell transistor with built-in voltage clamp 失效
标题翻译：带内置电压钳位的闭合单元晶体管
公开(公告)号：US5136349A
公开(公告)日：1992-08-04
申请号：US597118
申请日：1990-10-12
申请人： Hamza Yilmaz , Izak Bencuya
发明人： Hamza Yilmaz , Izak Bencuya
IPC分类号： H01L21/331 , H01L21/336 , H01L27/04 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/739 , H01L29/745 , H01L29/78
CPC分类号： H01L29/66712 , H01L29/0626 , H01L29/0688 , H01L29/0696 , H01L29/1095 , H01L29/66333 , H01L29/7395 , H01L29/7455 , H01L29/7808 , H01L29/4238
摘要： A power transistor takes advantage of the lower breakdown voltage capability of a spherical junction. A clamping region having a spherical shape is provided in the gater region of an enclosed transistor cell. The clamping region has a lower breakdown voltage than do the active portions of the transistor cell. Both a DMOSFET and an IGBT transistor may be provided with the clamping region. The clamping region is a zener diode in the case of the DMOSFET, and is a bipolar junction transistor in the case of the insulated gate bipolar transistor. The clamping region is preferably an island in the center of each cell of a closed cell structure.

9. 发明授权

US4543706A Fabrication of junction field effect transistor with filled grooves 失效
标题翻译：具有填充沟槽的结型场效应晶体管的制造
公开(公告)号：US4543706A
公开(公告)日：1985-10-01
申请号：US583514
申请日：1984-02-24
申请人： Izak Bencuya , Adrian I. Cogan
发明人： Izak Bencuya , Adrian I. Cogan
IPC分类号： H01L29/10 , H01L21/223 , H01L21/31
CPC分类号： H01L29/1066
摘要： Junction field effect transistor, specifically a static induction transistor and method of fabricating. A low resistivity N-type layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. The surface of the low resistivity N-type layer is coated with silicon nitride, portions of the silicon nitride are removed, and the silicon is etched to form parallel grooves with interposed ridges of silicon. Silicon dioxide is grown in the grooves, removed from the end walls of the grooves, and P-type zones are formed at the end walls of the grooves. Metal contacts are applied to the P-type zones at the end walls of the grooves. The grooves are filled with filler material and materials are etched away to produce a flat, planar surface with low resistivity N-type silicon of the ridges exposed in the surface and with filler material in the grooves also exposed at the surface. A large area metal contact is applied which extends across the surface and makes ohmic contact to the low resistivity N-type silicon of all the ridges.
摘要翻译：结型场效应晶体管，特别是静态感应晶体管及其制造方法。在低电阻N型硅衬底上生长的高电阻率N型外延层的表面形成低电阻率N型层。低电阻率N型层的表面涂覆有氮化硅，部分氮化硅被去除，并且蚀刻硅以形成具有插入的硅脊的平行凹槽。在凹槽中生长二氧化硅，从凹槽的端壁移除，并且在凹槽的端壁处形成P型区域。金属触点施加到槽的端壁处的P型区域。凹槽填充有填充材料，并且材料被蚀刻掉以产生平坦的平坦表面，其表面露出的脊的电阻率低的N型硅，并且槽中的填充材料也暴露在表面。施加大面积金属接触，其延伸穿过表面并与所有脊的低电阻率N型硅欧姆接触。

10. 发明授权

US09685806B2 Power connector with load current sensing 有权
公开(公告)号：US09685806B2
公开(公告)日：2017-06-20
申请号：US14538782
申请日：2014-11-11
申请人： Izak Bencuya
发明人： Izak Bencuya
IPC分类号： H02J7/02 , H02J7/00 , H01R13/66 , H01R13/703
CPC分类号： H02J7/0045 , H01R13/6683 , H01R13/7037 , H01R13/713 , H02J7/0031 , H02J7/0042 , H02J7/0047 , H02J2007/0037 , H02J2007/0049
摘要： A power connector for use in charging a battery of a device is provided. The power connector has an electromagnetic switch having terminals used to supply power from an external power source to a power adapter which is connected to the battery of the device. A power sensing circuit is coupled between the terminals of the electromagnetic switch and the power adapter, wherein the electromagnetic switch is configured to shut off power supplied to the power adapter when the power sensing circuit detects that the battery is fully charged. A reset mechanism is configured to mechanically activate the electromagnetic switch to start supplying power to the power adapter.

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