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1. 发明授权

US07885989B2 Encoding circuit and digital signal processing circuit 有权
标题翻译：编码电路和数字信号处理电路
公开(公告)号：US07885989B2
公开(公告)日：2011-02-08
申请号：US11614821
申请日：2006-12-21
申请人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
发明人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
IPC分类号： G06F7/00
CPC分类号： H04L1/0043
摘要： An encoding circuit is disclosed which comprises: a data-for-encoding storing register that stores n-bit data for encoding; a data-for-calculation storing register that stores m-bit data for calculation generated by shifting the data for encoding; a shifter that shifts the data for encoding stored in the data-for-encoding storing register, and shifts and inputs the shifted data into the data-for-calculation storing register; a first coefficient register that stores m-bit first coefficient data indicating a first coefficient for executing encoding; a first logic circuit that is inputted with the data for calculation stored in the data-for-calculation storing register and the first coefficient data stored in the first coefficient register and outputs the logical product for each bit of the data for calculation and the first coefficient data; and a second logic circuit that is inputted with m-bit data outputted from the first logic circuit and outputs the exclusive logical sum of the m-bit data as the encoded data.
摘要翻译：公开了一种编码电路，其包括：存储用于编码的n比特数据的用于编码的数据存储寄存器; 数据计算存储寄存器，其存储用于通过移位用于编码的数据而生成的用于计算的m位数据; 移位器，用于移位存储在数据编码存储寄存器中的用于编码的数据，并将移位的数据移位并输入到计算数据存储寄存器; 存储指示用于执行编码的第一系数的m位第一系数数据的第一系数寄存器; 输入存储在计算用数据存储寄存器中的用于计算的数据的第一逻辑电路和存储在第一系数寄存器中的第一系数数据，并输出用于计算的数据的每个位的逻辑积，并且第一系数数据; 以及第二逻辑电路，其输入从第一逻辑电路输出的m位数据，并输出作为编码数据的m位数据的异或逻辑和。

2. 发明申请

US20070150641A1 Bus Address Selecting Circuit and Bus Address Selecting Method 审中-公开
标题翻译：总线地址选择电路和总线地址选择方法
公开(公告)号：US20070150641A1
公开(公告)日：2007-06-28
申请号：US11614807
申请日：2006-12-21
申请人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
发明人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
IPC分类号： G06F12/06
CPC分类号： G06F13/1684 , G06F9/30043 , G06F9/30145 , G06F9/3824
摘要： A bus address selecting circuit is disclosed that selects addresses to be output to a first address bus connected to a first memory and a second address bus connected to a second memory, the bus address selecting circuit comprising an address output circuit that, based on a selecting bit composed of a predetermined plurality of bits in an instruction code, outputs addresses stored in first and second address registers out of a plurality of address registers as first and second addresses; and a bus selecting circuit that, based on predetermined higher-order n bits of at least one of the first and second addresses, outputs the first address to one of the first and second address buses and the second address to the other of the first and second address buses.
摘要翻译：公开了一种总线地址选择电路，其选择要输出到连接到第一存储器的第一地址总线的地址和连接到第二存储器的第二地址总线，总线地址选择电路包括地址输出电路，其基于选择在指令码中由预定的多个比特组成的比特，将从多个地址寄存器中存储的第一和第二地址寄存器中存储的地址作为第一和第二地址输出; 以及总线选择电路，其基于所述第一和第二地址中的至少一个的预定高阶n位，将所述第一地址输出到所述第一和第二地址总线中的一个，并将所述第二地址输出到所述第一和第二地址总线中的第一地址，第二地址总线。

3. 发明申请

US20070147137A1 Memory Control Circuit and Memory Control Method 有权
标题翻译：存储器控制电路和存储器控制方法
公开(公告)号：US20070147137A1
公开(公告)日：2007-06-28
申请号：US11614793
申请日：2006-12-21
申请人： Takashi Kuroda , Iwao Honda , Noriyuki Tomita , Hideki Ohashi
发明人： Takashi Kuroda , Iwao Honda , Noriyuki Tomita , Hideki Ohashi
IPC分类号： G11C7/10
CPC分类号： G06F12/04
摘要： A memory control circuit that controls m (=L/k) memories (first to mth memories), each of which has a k-bit width, the m memories storing data having a data width (D bits) of an integral multiple of k bits up to L bits, the circuit comprising: an address input circuit that determines a memory (nth memory) storing a first k bits of the data among the m memories, based on a start-position specification address which is a predetermined j bits of an A-bit address indicating a storage destination of the data, and inputs to the nth to mth memories a first specification address for specifying a storage destination of the data, the first specification address being an A-j bits of the A-bit address, which is the A-bit address without the predetermined j bits thereof, and inputs to the first to (n−1)th memories a second specification address obtained by adding one to the first specification address; a data input circuit that inputs a plurality of pieces of divided data obtained by dividing the data into k-bit data to the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address; a data output circuit that reads the plurality of pieces of divided data from the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, the number of the memories corresponding to the data width of the data, and outputs the read plurality of pieces of divided data as the data, based on the start-position specification address; and a memory selecting circuit that makes the D/k memories readable/writable, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address and the data width of the data.
摘要翻译：一种存储器控制电路，其控制具有k比特宽度的m（= L / k）个存储器（第一至第m个存储器），m个存储器存储具有k的整数倍的数据宽度（D比特）的数据该位电路包括：地址输入电路，其基于作为预定的j位的起始位置指定地址，确定在m个存储器中存储数据的前k位的存储器（第n个存储器）指示数据的存储目的地的A位地址，并且向第n至第m存储器输入用于指定数据的存储目的地的第一指定地址，第一指定地址是A位地址的Aj位，其中是没有其预定j比特的A比特地址，并且向第一到第（n-1）个存储器输入通过将一个加到第一指定地址而获得的第二指定地址; 数据输入电路，按照第n〜第m个存储器和第1〜第（n-1）个存储器的顺序，分别输入将数据分割成k位数据而得到的多条划分数据在起始位置指定地址; 数据输出电路，按照第n至第m个存储器和第1至第（n-1）个存储器的顺序从存储器分别读取多个划分的数据，对应于数据宽度的存储器的数量并根据开始位置指定地址输出读取的多条分割数据作为数据; 以及存储器选择电路，其基于开始位置指定地址和数据宽度，以第n至第m个存储器和第一至第（n-1）个存储器的顺序，使D / k存储器可读/可写数据。

4. 发明申请

US20070146194A1 Encoding Circuit and Digital Signal Processing Circuit 有权
标题翻译：编码电路和数字信号处理电路
公开(公告)号：US20070146194A1
公开(公告)日：2007-06-28
申请号：US11614821
申请日：2006-12-21
申请人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
发明人： Iwao Honda , Hideki Ohashi , Takashi Kuroda , Noriyuki Tomita
IPC分类号： G08C19/12
CPC分类号： H04L1/0043
摘要： An encoding circuit is disclosed which comprises: a data-for-encoding storing register that stores n-bit data for encoding; a data-for-calculation storing register that stores m-bit data for calculation generated by shifting the data for encoding; a shifter that shifts the data for encoding stored in the data-for-encoding storing register, and shifts and inputs the shifted data into the data-for-calculation storing register; a first coefficient register that stores m-bit first coefficient data indicating a first coefficient for executing encoding; a first logic circuit that is inputted with the data for calculation stored in the data-for-calculation storing register and the first coefficient data stored in the first coefficient register and outputs the logical product for each bit of the data for calculation and the first coefficient data; and a second logic circuit that is inputted with m-bit data outputted from the first logic circuit and outputs the exclusive logical sum of the m-bit data as the encoded data.
摘要翻译：公开了一种编码电路，其包括：存储用于编码的n比特数据的用于编码的数据存储寄存器; 数据计算存储寄存器，其存储用于通过移位用于编码的数据而生成的用于计算的m位数据; 移位器，用于移位存储在数据编码存储寄存器中的用于编码的数据，并将移位的数据移位并输入到计算数据存储寄存器; 存储指示用于执行编码的第一系数的m位第一系数数据的第一系数寄存器; 输入存储在计算用数据存储寄存器中的用于计算的数据的第一逻辑电路和存储在第一系数寄存器中的第一系数数据，并输出用于计算的数据的每个位的逻辑积，并且第一系数数据; 以及第二逻辑电路，其输入从第一逻辑电路输出的m位数据，并输出作为编码数据的m位数据的异或逻辑和。

5. 发明授权

US07440338B2 Memory control circuit and memory control method 有权
标题翻译：存储器控制电路和存储器控制方法
公开(公告)号：US07440338B2
公开(公告)日：2008-10-21
申请号：US11614793
申请日：2006-12-21
申请人： Takashi Kuroda , Iwao Honda , Noriyuki Tomita , Hideki Ohashi
发明人： Takashi Kuroda , Iwao Honda , Noriyuki Tomita , Hideki Ohashi
IPC分类号： G11C7/10
CPC分类号： G06F12/04
摘要： A memory control circuit that controls m (=L/k) memories (first to mth memories), each of which has a k-bit width, the m memories storing data having a data width (D bits) of an integral multiple of k bits up to L bits, the circuit comprising: an address input circuit that determines a memory (nth memory) storing a first k bits of the data among the m memories, based on a start-position specification address which is a predetermined j bits of an A-bit address indicating a storage destination of the data, and inputs to the nth to mth memories a first specification address for specifying a storage destination of the data, the first specification address being an A-j bits of the A-bit address, which is the A-bit address without the predetermined j bits thereof, and inputs to the first to (n−1)th memories a second specification address obtained by adding one to the first specification address; a data input circuit that inputs a plurality of pieces of divided data obtained by dividing the data into k-bit data to the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address; a data output circuit that reads the plurality of pieces of divided data from the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, the number of the memories corresponding to the data width of the data, and outputs the read plurality of pieces of divided data as the data, based on the start-position specification address; and a memory selecting circuit that makes the D/k memories readable/writable, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address and the data width of the data.
摘要翻译：一种存储器控制电路，其控制具有k比特宽度的m（= L / k）个存储器（第一至第m个存储器），m个存储器存储具有k的整数倍的数据宽度（D比特）的数据该位电路包括：地址输入电路，其基于作为预定的j位的起始位置指定地址，确定在m个存储器中存储数据的前k位的存储器（第n个存储器）指示数据的存储目的地的A位地址，并且向第n至第m存储器输入用于指定数据的存储目的地的第一指定地址，第一指定地址是A位地址的Aj位，其中是没有其预定j比特的A比特地址，并且向第一到第（n-1）个存储器输入通过将一个加到第一指定地址而获得的第二指定地址; 数据输入电路，按照第n〜第m个存储器和第1〜第（n-1）个存储器的顺序，分别输入将数据分割成k位数据而得到的多条划分数据在起始位置指定地址; 数据输出电路，按照第n至第m个存储器和第1至第（n-1）个存储器的顺序从存储器分别读取多个划分的数据，对应于数据宽度的存储器的数量并根据开始位置指定地址输出读取的多条分割数据作为数据; 以及存储器选择电路，其基于开始位置指定地址和数据宽度，以第n至第m个存储器和第一至第（n-1）个存储器的顺序，使D / k存储器可读/可写数据。

6. 发明申请

US20070242533A1 Memory Access Apparatus 有权
标题翻译：存储器访问装置
公开(公告)号：US20070242533A1
公开(公告)日：2007-10-18
申请号：US11734749
申请日：2007-04-12
申请人： Kazuhiro Nakamuta , Iwao Honda , Takashi Kuroda
发明人： Kazuhiro Nakamuta , Iwao Honda , Takashi Kuroda
IPC分类号： G11C7/10
CPC分类号： G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C8/06
摘要： A memory access apparatus reading data from a memory, the memory including a terminal that address information is input to, a terminal that a clock signal changing at a predetermined cycle is input to, a terminal that a read command is input to, and a terminal that outputs data stored at an address identified by the address information at a timing of the clock signal changing from one level to the other level in accordance with the read command, the memory access apparatus comprising: an address information output unit that outputs the address information and the read command at a first timing of the clock signal changing from the one level to the other level; and a read data storage unit that stores data output from the memory at a second timing after the first timing of the clock signal changing from the one level to the other level, the read data storage unit storing the data at a third timing after the second timing of the clock signal changing from the one level to the other level.
摘要翻译：从存储器读取数据的存储器访问装置，包括输入地址信息的终端的存储器，输入了以预定周期改变的时钟信号的终端，读取命令被输入的终端，以及终端根据读取命令，在时钟信号从一个电平变化到另一个电平的定时，输出存储在由地址信息识别的地址的数据，该存储器访问装置包括：地址信息输出单元，其输出地址信息以及所述读取命令在所述时钟信号从所述一个级别改变到另一个级别的第一定时; 以及读取数据存储单元，其在时钟信号从一个电平变化到另一个电平的第一定时之后的第二定时存储从存储器输出的数据，读取数据存储单元在第二时间之后的第三定时存储数据时钟信号从一个电平变化到另一个电平的时序。

7. 发明授权

US07480188B2 Memory Access apparatus 有权
标题翻译：存储器访问装置
公开(公告)号：US07480188B2
公开(公告)日：2009-01-20
申请号：US11734749
申请日：2007-04-12
申请人： Kazuhiro Nakamuta , Iwao Honda , Takashi Kuroda
发明人： Kazuhiro Nakamuta , Iwao Honda , Takashi Kuroda
IPC分类号： G11C7/10
CPC分类号： G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C8/06
摘要： A memory access apparatus reading data from a memory, the memory including a terminal that address information is input to, a terminal that a clock signal changing at a predetermined cycle is input to, a terminal that a read command is input to, and a terminal that outputs data stored at an address identified by the address information at a timing of the clock signal changing from one level to the other level in accordance with the read command, the memory access apparatus comprising: an address information output unit that outputs the address information and the read command at a first timing of the clock signal changing from the one level to the other level; and a read data storage unit that stores data output from the memory at a second timing after the first timing of the clock signal changing from the one level to the other level, the read data storage unit storing the data at a third timing after the second timing of the clock signal changing from the one level to the other level.
摘要翻译：从存储器读取数据的存储器访问装置，包括输入地址信息的终端的存储器，输入了以预定周期改变的时钟信号的终端，读取命令被输入的终端，以及终端根据读取命令，在时钟信号从一个电平变化到另一个电平的定时，输出存储在由地址信息识别的地址的数据，该存储器访问装置包括：地址信息输出单元，其输出地址信息以及所述读取命令在所述时钟信号从所述一个级别改变到另一个级别的第一定时; 以及读取数据存储单元，其在时钟信号从一个电平变化到另一个电平的第一定时之后的第二定时存储从存储器输出的数据，读取数据存储单元在第二时间之后的第三定时存储数据时钟信号从一个电平变化到另一个电平的时序。

8. 发明授权

US09284426B2 Hard coat film and curable resin composition for hard coat layer 有权
标题翻译：用于硬涂层的硬涂膜和可固化树脂组合物
公开(公告)号：US09284426B2
公开(公告)日：2016-03-15
申请号：US12580406
申请日：2009-10-16
申请人： Tomoyuki Horio , Takashi Kuroda , Emi Shimano , Kana Yamamoto , Yoshiko Kiyohara , Keiko Tasaki
发明人： Tomoyuki Horio , Takashi Kuroda , Emi Shimano , Kana Yamamoto , Yoshiko Kiyohara , Keiko Tasaki
IPC分类号： B32B5/16 , C08K3/34 , C08J7/04
CPC分类号： C08J7/047 , C08J2301/12 , C08J2433/00 , Y10T428/259
摘要： A curable resin composition for a hard coat layer capable of forming a hard coat layer having high hardness even with thin thickness and/or excellent in abrasion resistance and hardness, and a hard coat film using the curable resin composition.
摘要翻译：能够形成硬度均匀且硬度高，耐磨耗性和硬度优异的硬涂层的硬涂层用固化性树脂组合物和使用该固化性树脂组合物的硬涂膜。

9. 发明授权

US08730499B2 Image forming apparatus, control method therefor, and storage medium 有权
标题翻译：图像形成装置及其控制方法和存储介质
公开(公告)号：US08730499B2
公开(公告)日：2014-05-20
申请号：US12939890
申请日：2010-11-04
申请人： Takashi Kuroda
发明人： Takashi Kuroda
IPC分类号： G06F3/12 , G06K15/00
CPC分类号： G06F3/1285 , G03G15/502 , G06F3/1204 , G06F3/1208 , G06F3/1256 , H04N1/00411 , H04N1/00416 , H04N1/00435 , H04N1/0044 , H04N1/00458 , H04N1/00466 , H04N1/00469 , H04N2201/0094
摘要： When a preview image is displayed, an area on which a certain finishing process is executed is automatically enlarged and displayed. A control method for controlling an image forming apparatus including a display unit for previewing print results obtained by printing print information to be printed, the control method comprising: determining a preview position and a preview magnification rate of the print results to be displayed on the display unit, based on a post-processing setting for the print information; and controlling a preview of the print results to be displayed on the display unit, based on the determined preview position and preview magnification rate.
摘要翻译：当显示预览图像时，自动放大并显示执行某个精加工处理的区域。一种用于控制图像形成装置的控制方法，包括：用于预览通过打印要打印的打印信息而获得的打印结果的显示单元，所述控制方法包括：确定要在显示器上显示的打印结果的预览位置和预览放大率基于打印信息的后处理设置; 以及基于所确定的预览位置和预览放大率来控制要在显示单元上显示的打印结果的预览。

10. 发明申请

US20090251642A1 RETARDATION FILM, BRIGHTNESS ENHANCEMENT FILM, POLARIZING PLATE, PRODUCING METHOD OF A RETARDATION FILM, AND LIQUID CRYSTAL DISPLAY 审中-公开
标题翻译：延迟膜，亮度增强膜，极化板，延迟膜的制造方法和液晶显示
公开(公告)号：US20090251642A1
公开(公告)日：2009-10-08
申请号：US12374113
申请日：2007-07-17
申请人： Runa Nakamura , Hiroki Nakagawa , Takashi Kuroda , Yuya Inomata , Masanori Fukuda
发明人： Runa Nakamura , Hiroki Nakagawa , Takashi Kuroda , Yuya Inomata , Masanori Fukuda
IPC分类号： G02F1/1347 , G02F1/13 , B29D7/01 , G02B1/08
CPC分类号： G02B5/3016 , B32B23/04 , B32B23/08 , B32B23/14 , B32B23/20 , B32B27/18 , B32B27/281 , B32B27/308 , B32B27/325 , B32B27/40 , B32B2307/40 , B32B2307/412 , B32B2307/418 , B32B2307/42 , B32B2307/54 , B32B2307/706 , B32B2307/724 , B32B2307/7242 , B32B2457/202 , G02F1/133634 , G02F2201/50 , G02F2413/02 , G02F2413/11 , G02F2413/12
摘要： A retardation film that is used as a polarizing plate protective film, thereby making it possible to yield a polarizing plate which is very good in durability and has a viewing angle compensation function. The retardation film has: an optical anisotropic film, in which a relation of nx>ny is realized between a refractive index “nx” in a slow axis direction of an in-plane direction and a refractive index “ny” in a fast axis direction of the in-plane direction; and a retardation layer formed on the optical anisotropic film and containing a liquid crystalline material, in which a relation of nx≦ny
摘要翻译：作为偏光板保护膜使用的延迟膜，能够得到耐久性良好且具有视角补偿功能的偏光板。相位差膜具有：光学各向异性膜，其中在面内方向的慢轴方向上的折射率“nx”与快轴方向的折射率“ny”之间实现nx> ny的关系的平面方向; 以及形成在光学各向异性膜上并含有液晶材料的延迟层，其中在任意方向“x”和“y”之间实现折射率“nx”和“ny”之间的nx <= ny

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