专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120105124A1 SEMICONDUCTOR APPARATUS, METHOD FOR DELAYING SIGNAL THEREOF, STACKED SEMICONDUCTOR MEMORY APPARATUS, AND METHOD FOR GENERATING SIGNAL THEREOF 有权
标题翻译：半导体装置，其延迟信号的方法，堆叠式半导体存储装置及其信号生成方法
公开(公告)号：US20120105124A1
公开(公告)日：2012-05-03
申请号：US12970882
申请日：2010-12-16
申请人： Heat Bit PARK , Kee Teok Park
发明人： Heat Bit PARK , Kee Teok Park
IPC分类号： H03H11/26
CPC分类号： G11C7/00 , G11C5/063 , G11C7/222
摘要： The semiconductor apparatus includes a reference delay value check unit configured to receive a source signal and delay the source signal to generate a reference delay signal; a process delay value check unit configured to receive the source signal and delay the source signal to generate a process delay signal; and a signal generation unit configured to receive the reference delay signal and the process delay signal, receive an input signal, and variably delay the input signal based on the reference delay signal and the process delay signal to generate an output signal.
摘要翻译：该半导体装置包括基准延迟值检查单元，被配置为接收源信号并延迟源信号以产生参考延迟信号; 处理延迟值检查单元，被配置为接收源信号并延迟源信号以产生处理延迟信号; 以及信号生成单元，被配置为接收参考延迟信号和处理延迟信号，接收输入信号，并且基于参考延迟信号和处理延迟信号可变地延迟输入信号以产生输出信号。

2. 发明申请

US20120131258A1 SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME 审中-公开
标题翻译：半导体存储器及其操作方法
公开(公告)号：US20120131258A1
公开(公告)日：2012-05-24
申请号：US13217421
申请日：2011-08-25
申请人： Heat Bit PARK
发明人： Heat Bit PARK
IPC分类号： G06F12/06
CPC分类号： G11C8/12
摘要： A semiconductor memory apparatus includes, inter alia, a master chip and a plurality of slave chips. Each of the slave chips includes a plurality of banks. A first reception signal, a first timing signal, a bank address signal, and a slice selection signal to the slave chips may be provided by a master chip. The slave chips include a slice determining unit configured to compare the slice selection signal and a slice code and generate a slice enable signal, and a bank selecting unit configured to receive the bank address signal in response to the first reception signal and the slice enable signal and generate a bank enable signal in response to the bank address signal and the first timing signal.
摘要翻译：一种半导体存储器装置尤其包括主芯片和多个从芯片。每个从属芯片包括多个存储体。主芯片可以提供第一接收信号，第一定时信号，存储体地址信号和从芯片的片选择信号。从芯片包括片确定单元，被配置为比较切片选择信号和切片码，并生成切片使能信号;以及存储体选择单元，被配置为响应于第一接收信号和切片使能信号接收存储体地址信号并响应于所述存储体地址信号和所述第一定时信号产生存储体使能信号。

3. 发明申请

US20110161753A1 SEMICONDUCTOR MEMORY APPARATUS INCLUDING DATA COMPRESSION TEST CIRCUIT 有权
标题翻译：半导体存储器包括数据压缩测试电路
公开(公告)号：US20110161753A1
公开(公告)日：2011-06-30
申请号：US12836519
申请日：2010-07-14
申请人： Heat Bit PARK , Tae Sik YUN
发明人： Heat Bit PARK , Tae Sik YUN
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G11C29/40
摘要： A semiconductor memory apparatus having stacked first and second chips includes a first chip test signal generation unit disposed in the first chip and configured to generate a first chip test signal in response to a first chip compression data determination signal in a test mode, a second chip test signal generation unit disposed in the second chip and configured to generate a second chip test signal in response to a second chip compression data determination signal in the test mode, and a final data determination unit configured to generate a final test to signal in response to the first and second chip test signals in the test mode.
摘要翻译：具有堆叠的第一和第二芯片的半导体存储器件包括：第一芯片测试信号生成单元，设置在第一芯片中，并且被配置为响应于测试模式中的第一芯片压缩数据确定信号产生第一芯片测试信号;第二芯片测试信号生成单元，其设置在所述第二芯片中，并且被配置为响应于所述测试模式中的第二芯片压缩数据确定信号而产生第二芯片测试信号，以及最终数据确定单元，被配置为产生响应于第一和第二芯片测试信号处于测试模式。

4. 发明申请

US20120212990A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20120212990A1
公开(公告)日：2012-08-23
申请号：US13167963
申请日：2011-06-24
申请人： Heat Bit PARK , Kang Seol Lee
发明人： Heat Bit PARK , Kang Seol Lee
IPC分类号： G11C5/06
CPC分类号： G06F13/385
摘要： A semiconductor apparatus includes a multi-chip module which multi-chip module comprises a first and a second chips. The semiconductor apparatus comprises a first data line in the first chip to carry first read data; a first controller, in the first chip, configured to generate first output data on a first output data line in the first chip based on the first read data transmitted from the first data line; a first data transmitter configured to electrically connect the first output data line to the second chip.
摘要翻译：半导体装置包括多芯片模块，该多芯片模块包括第一芯片和第二芯片。半导体装置包括第一芯片中的第一数据线，以承载第一读取数据; 第一芯片中的第一控制器被配置为基于从第一数据线发送的第一读取数据在第一芯片中的第一输出数据线上生成第一输出数据; 第一数据发射机，被配置为将所述第一输出数据线电连接到所述第二芯片。

5. 发明申请

US20110103162A1 SEMICONDUCTOR MEMORY APPARATUS 审中-公开
标题翻译：半导体存储器
公开(公告)号：US20110103162A1
公开(公告)日：2011-05-05
申请号：US12650882
申请日：2009-12-31
申请人： Heat Bit PARK
发明人： Heat Bit PARK
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C5/063 , G11C5/025 , G11C7/18 , G11C2207/002
摘要： A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: a plurality of memory banks disposed at a predetermined distance from each other in a first direction; a common column selection control unit disposed at an outside region of the plurality of memory banks in the first direction, and configured to commonly control access to column areas of the plurality of memory banks; and a common column selection signal transmission line configured to transfer a column selection signal for controlling data access to the corresponding memory cells of the plurality of memory banks. The common column selection control unit generates the column selection signal, and a delay length of the column selection signal is adjusted based on a length of a transmission path of the column selection signal.
摘要翻译：提供半导体存储装置。半导体存储装置包括：沿第一方向彼此隔开预定距离地设置的多个存储体; 公共列选择控制单元，设置在所述多个存储体的第一方向的外部区域，并且被配置为共同地控制对所述多个存储体的列区域的访问; 以及公共列选择信号传输线，被配置为传送用于控制数据访问的列选择信号到多个存储体的相应存储单元。公共列选择控制单元产生列选择信号，并且基于列选择信号的传输路径的长度来调整列选择信号的延迟长度。

6. 发明申请

US20110242907A1 SEMICONDUCTOR MEMORY APPARATUS AND READ/WRITE CONTROL METHOD THEREOF 有权
标题翻译：半导体存储器及其读/写控制方法
公开(公告)号：US20110242907A1
公开(公告)日：2011-10-06
申请号：US12970915
申请日：2010-12-16
申请人： Heat Bit PARK
发明人： Heat Bit PARK
IPC分类号： G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C5/04
摘要： A semiconductor memory apparatus includes: a read/write control unit configured to generate a write control signal and a read control signal using internal signals generated through separate signal paths in response to a write command and a read command respectively; and a plurality of ranks configured to perform a write operation or read operation according to the write control signal or the read control signal.
摘要翻译：半导体存储装置包括：读/写控制单元，被配置为分别响应于写入命令和读取命令，使用通过单独的信号路径产生的内部信号来产生写入控制信号和读取控制信号; 以及多个等级，其被配置为根据写入控制信号或读取控制信号执行写入操作或读取操作。

7. 发明申请

US20110103160A1 SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器
公开(公告)号：US20110103160A1
公开(公告)日：2011-05-05
申请号：US12650666
申请日：2009-12-31
申请人： Heat Bit PARK
发明人： Heat Bit PARK
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/02 , G11C7/18
摘要： A semiconductor memory apparatus is provided. The semiconductor memory apparatus comprises: first and second memory banks located a predetermined distance from each other in a first direction; a common column selection control unit located at an outside region in the first and second memory banks in the first direction, and configured to commonly control access to column areas in the first and second memory banks and generate a column selection signal that controls data access to the corresponding memory cells in the first and second memory banks; a first data read/write unit configured to sense and amplify read data transferred from the first memory bank and transfer write data to the first memory bank; and a second data read/write unit configured to sense and amplify read data transferred from the second memory bank and transfer write data to the second memory bank. The first data read/write unit and the second data read/write unit are located so as to be spaced from each other in the first direction with the memory bank interposed therebetween.
摘要翻译：提供半导体存储装置。半导体存储装置包括：第一和第二存储体，其位于第一方向上彼此预定的距离; 公共列选择控制单元，位于第一和第二存储体中的第一方向上的外部区域，并且被配置为共同地控制对第一和第二存储体中的列区域的访问，并且生成控制数据访问的列选择信号第一和第二存储体中的对应的存储单元; 第一数据读/写单元，被配置为检测和放大从第一存储体传送的读数据并将写数据传送到第一存储体; 以及第二数据读/写单元，被配置为感测和放大从第二存储体传送的读数据并将写数据传送到第二存储体。第一数据读/写单元和第二数据读/写单元被定位成在第一方向上彼此间隔开，存储体插入其间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式