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1. 发明授权

US6127215A Deep pivot mask for enhanced buried-channel PFET performance and reliability 失效
标题翻译：深层掩模，增强埋地通道PFET性能和可靠性
公开(公告)号：US6127215A
公开(公告)日：2000-10-03
申请号：US181964
申请日：1998-10-29
申请人： Hans-Oliver Joachim , Jack A. Mandelman , Rajesh Rengarajan
发明人： Hans-Oliver Joachim , Jack A. Mandelman , Rajesh Rengarajan
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0928 , H01L21/76237
摘要： A semiconductor structure comprises first gate conductors which wrap around N-wells of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do not wrap around P-wells of surface-channel N-type metal oxide semiconductor field effect transistors and a method of manufacturing the same comprises forming insulators adjacent each of the N-wells and the P-wells, protecting the N-wells with a patterned mask, forming first divots in areas of the insulators adjacent the N-wells and forming second divots in areas of the insulators adjacent P-wells, wherein the first divots have a greater depth than the second divots.
摘要翻译：半导体结构包括第一栅极导体，其围绕掩埋沟道P型金属氧化物半导体场效应晶体管的N阱和不包围表面沟道N型金属氧化物半导体场效应的P阱的第二栅极导体晶体管及其制造方法包括在每个N阱和P阱附近形成绝缘体，用图案化掩模保护N阱，在与N阱相邻的绝缘体的区域中形成第一个纹理并形成第二个邻近P型井的绝缘体区域中的裂缝，其中第一层岩石具有比第二岩层更深的深度。

2. 发明授权

US06501131B1 Transistors having independently adjustable parameters 有权
标题翻译：晶体管具有可独立调节的参数
公开(公告)号：US06501131B1
公开(公告)日：2002-12-31
申请号：US09359291
申请日：1999-07-22
申请人： Rama Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
发明人： Rama Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823807 , H01L29/66492 , H01L29/66537 , H01L29/66583
摘要： The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget is further significantly reduced by a device structure which allows a reduced gap aspect ratio while maintaining low sheet resistance values. A reduced gap aspect ratio also relaxes the need for highly reflowable dielectric materials and also facilitates the use of angled source-drain (S-D) and halo implants. Also provided is a novel structure and process for producing a MOSFET channel, lateral doping profile which suppresses short channel effects while providing low S-D junction capacitance and leakage, as well as immunity to hot-carrier effects. This also affords the potential for reduction in the contact stud-to-gate conductor capacitance, because borderless contacts can be formed with an oxide gate sidewall spacer. As a result, the S-D junctions can be doped independently of the gate conductor doping, more easily allowing a variety of MOSFET structures.
摘要翻译：制造半导体器件如MOSFET的工艺规则被修改，以提供遵循常规栅极侧壁氧化步骤的双重功能掺杂，大大降低了热预算和硼渗透问题。通过允许减小的间隙宽高比同时保持低的薄层电阻值的装置结构，热预算的关注进一步显着降低。减小的间隙宽高比也放松了对高回流电介质材料的需要，并且还有助于使用倾斜的源漏（S-D）和晕轮植入物。还提供了用于产生MOSFET沟道，横向掺杂分布的新型结构和工艺，其抑制短沟道效应，同时提供低S-D结电容和泄漏，以及对热载流子效应的抗扰性。这也提供了减小接触柱对栅极导体电容的可能性，因为可以用氧化物栅极侧壁间隔物形成无边界接触。结果，S-D结可以独立于栅极导体掺杂掺杂，更容易地允许各种MOSFET结构。

3. 发明授权

US06740920B2 Vertical MOSFET with horizontally graded channel doping 失效
标题翻译：具有水平梯度通道掺杂的垂直MOSFET
公开(公告)号：US06740920B2
公开(公告)日：2004-05-25
申请号：US10096219
申请日：2002-03-11
申请人： Dureseti Chidambarrao , Kil-Ho Lee , Jack A. Mandelman , Kevin McStay , Rajesh Rengarajan
发明人： Dureseti Chidambarrao , Kil-Ho Lee , Jack A. Mandelman , Kevin McStay , Rajesh Rengarajan
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L21/26586 , H01L27/10838 , H01L29/66666 , H01L29/7827
摘要： Body effects in vertical MOSFET transistors are considerably reduced and other device parameters are unaffected in a vertical transistor having a threshold implant with a peak at the gate and an implant concentration distribution that declines rapidly away from the gate to a plateau having a low p-well concentration value. A preferred embodiment employs two body implants—an angled implant having a peak at the gate that sets the Vt and a laterally uniform low dose implant that sets the well dopant concentration.
摘要翻译：在垂直MOSFET晶体管中的体效应显着降低，并且在具有在栅极处具有峰值的阈值注入的垂直晶体管中的其它器件参数不受影响，并且注入浓度分布从栅极快速下降到具有低p阱的平台浓度值。优选实施例采用两个体植入物 - 成角度的植入物，其在浇口处具有设置Vt的峰值，以及设置阱掺杂剂浓度的横向均匀的低剂量注入。

4. 发明授权

US06426247B1 Low bitline capacitance structure and method of making same 失效
标题翻译：低位线电容结构及其制作方法
公开(公告)号：US06426247B1
公开(公告)日：2002-07-30
申请号：US09764824
申请日：2001-01-17
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
IPC分类号： H01L21338
CPC分类号： H01L27/10888 , H01L23/485 , H01L27/10861 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a memory device having low bitline capacitance, comprising: providing a gate conductor stack structure on a silicon substrate, said gate stack structure having a gate oxide layer, a polysilicon layer, a silicide layer, and a top dielectric nitride layer; oxidizing sidewalls of said gate oxide stack; forming sidewall spacers on the sidewalls of said gate conductor stack, said sidewall spacers comprising a thin layer of nitride having a thickness ranging from about 50 to about 250 angstroms; overlaying the gate structure with a thin nitride liner having a thickness ranging from about 25 to about 150 angstroms; depositing an insulative oxide layer over the gate structure; polishing the insulative oxide layer down to the level of the nitride liner of the gate structure; patterning and etching the insulative oxide layer to expose said nitride liner; forming second sidewall spacers over said first sidewall spacers, said second sidewall spacers comprising an oxide layer having a thickness ranging from about 100 to about 400 angstroms; and, depositing and planarizing a layer of polysilicon covering said gate structure and the sidewall spacers.
摘要翻译：一种用于形成具有低位线电容的存储器件的方法，包括：在硅衬底上提供栅极导体堆叠结构，所述栅堆叠结构具有栅极氧化层，多晶硅层，硅化物层和顶部电介质氮化物层; 氧化所述栅极氧化层的侧壁; 在所述栅极导体堆叠的侧壁上形成侧壁间隔物，所述侧壁间隔物包括厚度范围为约50至约250埃的薄氮化物层; 用具有约25至约150埃的厚度的薄氮化物衬垫覆盖栅极结构; 在栅极结构上沉积绝缘氧化物层; 将绝缘氧化物层抛光到栅极结构的氮化物衬垫的水平面; 图案化和蚀刻绝缘氧化物层以暴露所述氮化物衬垫; 在所述第一侧壁间隔物上形成第二侧壁间隔物，所述第二侧壁间隔物包括厚度范围为约100至约400埃的氧化物层; 并且沉积和平坦化覆盖所述栅极结构和侧壁间隔物的多晶硅层。

5. 发明授权

US06323103B1 Method for fabricating transistors 有权
标题翻译：晶体管制造方法
公开(公告)号：US06323103B1
公开(公告)日：2001-11-27
申请号：US09175267
申请日：1998-10-20
申请人： Rajesh Rengarajan , Jochen Beintner , Ulrike Gruening , Hans-Oliver Joachim
发明人： Rajesh Rengarajan , Jochen Beintner , Ulrike Gruening , Hans-Oliver Joachim
IPC分类号： H01L218238
CPC分类号： H01L21/823878 , H01L21/762
摘要： A method is provided for fabricating a first and second MOSFET transistors in different electrically isolated active areas of a semiconductor body, each one of the transistors having a plurality of layers. A first gate oxide layer and a first poly-crystalline silicon layer are deposited over the semiconductor body over the active areas. Trenches are etched in said first gate oxide and poly-crystalline silicon layers and said semiconductor body to delineate the first and second active areas, thereby forming first delineated gate oxide layer and poly-crystalline silicon layers coextensive with the first active area. Material is deposited in said trenches to form the active area isolations, the active area isolations having a top surface above said semiconductor body. A masking layer is then formed over said first and second active areas and selective portions of it are removed to expose said second active area. The masking layer and the active area isolations together form a mask defining an opening coextensive with the second active area with the active area isolations defining said opening. Material through the opening to form a second gate oxide layer and a second poly-crystalline layer, such second layer and second poly-crystalline layer being coextensive with the second active area. The first transistor with the first delineated gate oxide and poly-crystalline layer as a pair of the plurality of layers of the first transistor and the second transistor with the second gate oxide layer and second poly-crystalline layer as a pair of the plurality of layers of the second transistor.
摘要翻译：提供了一种用于在半导体主体的不同电隔离有源区中制造第一和第二MOSFET晶体管的方法，每个晶体管具有多个层。第一栅极氧化物层和第一多晶硅层沉积在半导体主体上方的有源区域上。在所述第一栅极氧化物和多晶硅层和所述半导体本体中蚀刻沟槽以描绘第一和第二有源区，从而形成与第一有源区共同延伸的第一划定的栅极氧化物层和多晶硅层。材料沉积在所述沟槽中以形成有源区隔离，所述有源区隔离在所述半导体本体上方具有顶表面。然后在所述第一和第二有源区上形成掩模层，并且去除其选择性部分以暴露所述第二有源区。屏蔽层和有源区隔离一起形成掩模，其限定与第二有源区域共同延伸的开口，其中限定所述开口的有源区隔离。通过开口的材料形成第二栅氧化层和第二多晶层，这种第二层和第二多晶层与第二有源区共同延伸。第一晶体管，其具有第一划定的栅极氧化物和多晶层作为第一晶体管的多个层和第二晶体管的一对，其中第二栅极氧化物层和第二多晶层作为一对多个层的第二晶体管。

6. 发明申请

US20120104511A1 DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS 有权
标题翻译： CMOS混合方向的双路隔离
公开(公告)号：US20120104511A1
公开(公告)日：2012-05-03
申请号：US13349203
申请日：2012-01-12
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L27/092
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
摘要翻译：本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第第一深度用于隔离相同极性的设备。本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

7. 发明申请

US20080290379A1 DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS 有权
标题翻译： CMOS混合方向的双路隔离
公开(公告)号：US20080290379A1
公开(公告)日：2008-11-27
申请号：US12169991
申请日：2008-07-09
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L21/8234 , H01L29/04
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
摘要翻译：本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第第一深度用于隔离相同极性的设备。本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

8. 发明申请

US20080044966A1 ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXIAL COMPRESSIVE STRAIN 有权
公开(公告)号：US20080044966A1
公开(公告)日：2008-02-21
申请号：US11924024
申请日：2007-10-25
申请人： Victor Chan , Massimo Fischetti , John Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul Solomon , Chun-yung Sung , Min Yang
发明人： Victor Chan , Massimo Fischetti , John Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul Solomon , Chun-yung Sung , Min Yang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7846 , H01L29/78684
摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

9. 发明授权

US6074903A Method for forming electrical isolation for semiconductor devices 失效
标题翻译：用于形成半导体器件的电隔离的方法
公开(公告)号：US6074903A
公开(公告)日：2000-06-13
申请号：US98203
申请日：1998-06-16
申请人： Rajesh Rengarajan , Hirofumi Inoue , Radhika Srinivasan , Jochen Beintner
发明人： Rajesh Rengarajan , Hirofumi Inoue , Radhika Srinivasan , Jochen Beintner
IPC分类号： H01L21/76 , H01L21/762 , H01L27/08 , H01L21/8238
CPC分类号： H01L21/76237
摘要： A method for forming a electrically isolated semiconductor devices in a silicon body. A trench is formed in a selected region of the body. A barrier material is deposited over sidewalls of the trench. Portions of the barrier material are removed from a first sidewall portion of the trench to expose such first sidewall portion of the trench while leaving portions of such barrier material on a second sidewall portion of the trench to form a barrier layer thereon. A dielectric material is deposited in the trench, a portion of dielectric material being deposited on the exposed first sidewall portion of the trench and another portion of such deposited dielectric material being deposited on the barrier material. The dielectric material is annealed in an oxidizing environment to densify such deposited dielectric material, the barrier layer inhibiting oxidation of the said second sidewall portion of the trench. A plurality of the semiconductor devices is formed in the silicon body with such devices being electrically isolated by the dielectric material in the trench.
摘要翻译：一种用于在硅体中形成电绝缘的半导体器件的方法。在身体的选定区域中形成沟槽。阻挡材料沉积在沟槽的侧壁上。阻挡材料的一部分从沟槽的第一侧壁部分被去除以暴露沟槽的这种第一侧壁部分，同时将这种阻挡材料的一部分留在沟槽的第二侧壁部分上以在其上形成阻挡层。电介质材料沉积在沟槽中，介电材料的一部分沉积在暴露的沟槽的第一侧壁部分上，另一部分沉积的介电材料沉积在阻挡材料上。电介质材料在氧化环境中退火以致密化这种淀积的介电材料，阻挡层阻止沟槽的所述第二侧壁部分的氧化。在硅体中形成多个半导体器件，这些器件通过沟槽中的电介质材料电隔离。

10. 发明授权

US08097516B2 Dual trench isolation for CMOS with hybrid orientations 有权
标题翻译：具有混合取向的CMOS的双沟槽隔离
公开(公告)号：US08097516B2
公开(公告)日：2012-01-17
申请号：US12169991
申请日：2008-07-09
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
摘要翻译：本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第第一深度用于隔离相同极性的设备。本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

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