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1. 发明专利

JP2000132985A SEMICONDUCTOR MEMORY APPARATUS AND DATA-PROCESSING APPARATUS 失效
公开(公告)号：JP2000132985A
公开(公告)日：2000-05-12
申请号：JP30506098
申请日：1998-10-27
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD , HITACHI ULSI SYS CO LTD
发明人： HARADA RYOJI , KASAI HIDEO , ETO JUN , KAWAJIRI YOSHIKI
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a technique for shortening a read time for memory cell data. SOLUTION: There are provided sense amplifiers MP1, MN1, MN2, MP2, MN3 for amplifying a signal transmitted from a bit line to a common line, a charge pull switch 21 for finishing a charge-pulling operation to an adjacent bit line selected prior to the bit line before the bit line is started to be precharged, and control logics G3, G4 for forming an operation control signal for the charge pull switch. Since the charge-pulling operation to the adjacent bit line selected prior to the bit line is completed before the bit line is started to be precharged, a read time for memory cell data is shortened with influences of a parasitic capacitance between bit lines being avoided.

2. 发明专利

JPH113599A SEMICONDUCTOR MEMORY AND DATA PROCESSING DEVICE 失效
公开(公告)号：JPH113599A
公开(公告)日：1999-01-06
申请号：JP15469697
申请日：1997-06-12
申请人： HITACHI LTD , HITACHI TOKYO ELECTRONICS , HITACHI TOBU SEMICONDUCTOR LTD
发明人： SEKIGUCHI KAZUO , MATSUMOTO KENJI , KAWAJIRI YOSHIKI , HASEGAWA NAOHIRO , NAKANO YASUSHI
IPC分类号： G11C17/00 , G11C17/12
摘要： PROBLEM TO BE SOLVED: To improve yield by enlarging operation margin. SOLUTION: Two reference lines R1, R2 are provided and switches 73, 74 for switching synchronously the reference lines R1, R2 to bit line selection. View of line capacity of bit lines is made equal to view of line capacity of reference lines in the case of watching from a differential stage side by switching of the reference lines, enlarging operation margin is attained by reducing influence of line capacity.

3. 发明专利

JPH11265227A CONSTANT VOLTAGE GENERATING CIRCUIT AND POWER SUPPLY VOLTAGE LOWERING DETECTING CIRCUIT USING THE SAME, AND PULSE GENERATING CIRCUIT AT POWER-ON, AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME 失效
公开(公告)号：JPH11265227A
公开(公告)日：1999-09-28
申请号：JP6797698
申请日：1998-03-18
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： KASAI HIDEO , KAWAJIRI YOSHIKI , CHORI TORU
IPC分类号： G11C16/06 , G05F1/56 , G05F3/24 , H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a constant voltage generating circuit in which the increase of a layout area can be suppressed, and the power supply voltage and temperature dependency of an output voltage can be reduced, power supply voltage lowering detecting circuit using the same, pulse generating circuit at power-on, and semiconductor memory device using them. SOLUTION: In a flash memory constituted of a memory array and the peripheral circuit or the like, the constant voltage generating circuit VG is incorporated in the control circuit of the peripheral circuit, and this constant voltage generating circuit VG is constituted so that a P-type enhancement MOS transistor PET1, N-type depression MOS transistor NDT, and two level N-type enhancement MOS transistors NET1 and NET2 can be serially connected. The N-type enhancement MOS transistor PET1 is set so that the N-type depression MOS transistor NDT can be saturated area-operated, and an output voltage V set by the threshold voltages and the number of stages of the transistors NET1 and NET2 is generated from a connected node B.

4. 发明专利

JPH11306780A POWER SOURCE CIRCUIT, SEMICONDUCTOR STORAGE DEVICE, AND DATA PROCESSING APPARATUS 失效
公开(公告)号：JPH11306780A
公开(公告)日：1999-11-05
申请号：JP10742698
申请日：1998-04-17
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD , MITSUBISHI ELECTRIC CORP
发明人： CHORI TORU , KAWAJIRI YOSHIKI , TATEWAKI YASUHIKO
IPC分类号： G11C16/06 , G05F3/24
摘要： PROBLEM TO BE SOLVED: To realize a reduction in the area occupied by a chip of a voltage detecting circuit. SOLUTION: When a power source circuit includes a pumping circuit 4 for forming a predetermined voltage, a voltage detecting circuit 500 for detecting the output voltage of the pumping circuit and a comparison circuit 38 for comparing the detection result of the voltage detecting circuit 500 with a comparison voltage, the voltage detecting circuit 500 is configured by connecting in series a plurality of voltage-dividing transistors 23-32 for dividing the output voltage of the pumping circuit 4. The voltage detecting circuit 500 configured by connecting in series the plurality of voltage-dividing transistors 23-32 has a reduced layout area, as compared to a resistive voltage-dividing circuit in which a consumption current of the same level flows with the same resistance value, thereby reducing an area occupied by a chip of the voltage detecting circuit 500.

5. 发明专利

JPH11265986A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH11265986A
公开(公告)日：1999-09-28
申请号：JP8804098
申请日：1998-03-17
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： MURAKAMI HITOSHI , KASAI HIDEO , CHICHII MIKIO , KOSAKAI KENJI , KAWAJIRI YOSHIKI , ETO JUN
IPC分类号： H01L27/10 , H01L21/8247 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To achieve the low cost of flash memories and the like by enhancing the arranging efficiency of logic cells and wiring in logic circuit parts such as the flash memories, reducing the size of the chip, increasing the lines of the cells provided in the logic circuit parts at the same time and increasing the number of the logic cells that can be provided at the respective cell lines. SOLUTION: In the flash memory and the like having a memory array MARY and a logic circuit part LOGC and having gate layers SG and metal wiring layers M1 and M2 of the first layer and the second layer as the wiring layers, cell lines CL1-CL8 of the logic circuit part LOGC are arranged at the perpendicular direction for the rectangular close side in the arranging pattern of the memory array MARY, that is, the lower short side. At the same time, gate layers SG and first-layer metal wiring layers M1 are arranged as the wirings in the cell. As the power-supply wiring for each logic cell 1 and the wiring channel for the wiring between the cells, the first-layer metal wiring layer M1 is used. As the outgoing wiring between the logic cell and the wiring channel, the gate layer SG is used. Thus, the second metal wiring layer M2 can be arranged in the arbitral direction on the upper layer of the logic cell as the wiring between the cells.

6. 发明专利

DE69028617T2 未知
公开(公告)号：DE69028617T2
公开(公告)日：1997-04-03
申请号：DE69028617
申请日：1990-12-28
申请人： HITACHI LTD
发明人： WATANABE TAKAO , KIMURA KATSUTAKA , ITOH KIYOO , KAWAJIRI YOSHIKI
IPC分类号： G06F17/16 , G06N3/04 , G06F15/18 , G06N3/063 , G06N99/00 , G06F13/00 , G06F15/80
摘要： Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.

7. 发明专利

DE3688222T2 未知
公开(公告)号：DE3688222T2
公开(公告)日：1993-11-04
申请号：DE3688222
申请日：1986-07-10
申请人： HITACHI LTD
发明人： WATANABE TAKAO , KITUKAWA GORO , HORI RYOICHI , ITOH KIYOO , KAWAJIRI YOSHIKI , KAWAHARA TAKAYUKI
IPC分类号： G11C7/12 , G11C8/10 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/017 , H03K19/0175 , H03K19/0944 , H03K5/02 , H03K19/08 , H03K19/01 , H03K19/096 , G11C7/00
摘要： A semiconductor device of high integration density and low power consumption prevents the influence of the amplitude of an input signal upon the amplitude of an output signal in such a way that a preceding circuit (C) and a succeeding circuit (D) are endowed with different reference voltages.In an aspect of performance, the semiconductor device is constructed of a circuit which includes a bipolar transistor (26) and an insulated-gate field effect transistor (25, 27, 291, and which operates with reference to one or more voltages (B1), at least one of the reference voltages having a voltage value different from a reference operating voltage (VA) of a preceding circuit (CI which controls the above circuit.In another aspect of performance, first switching means is interposed between a first reference voltage and an input node of a driver circuit, and second switching means is interposed between an output of a preceding circuit and the input of the driver circuit, so that when an output signal of the preceding circuit is at a high level, the second switch is turned "on" while the first switch is turned "off" thereby to produce a still higher potential, and that when the output signal of the preceding circuit is at a low level, the second switch is turned "off" while the first switch is turned "on".The semiconductor device is suited to those circuits of a high-density DRAM and SRAM which use voltage limiters.

8. 发明专利

DE2946633A1 未知
公开(公告)号：DE2946633A1
公开(公告)日：1980-06-04
申请号：DE2946633
申请日：1979-11-19
申请人： HITACHI LTD
发明人： TANAKA HIROTOSHI , KAWAJIRI YOSHIKI , CHIBA KOUTSU , HORI RYOICHI , ITOH KIYOO
IPC分类号： G11C11/413 , G11C8/00 , G11C11/408 , G11C7/00
摘要： In a memory device, row and column decoders are connected through a common address signal line to an address buffer, and the row decoder is connected through a switch to the common address signal line. When the address buffer delivers a first address signal, the switch is turned on so that the first address signal is applied to both of the column and row decoders. The column decoder includes therein provision for disabling the column decoder when the first address signal is applied to column decoder. The column decoder therefore does not respond to the first address signal. Subsequently, when the address buffer delivers a second address signal, the switch is turned off so that the row decoder is not applied with the second address signal but the column decoder responds to the second address signal. Thus, the row and column address respond to the first and second address signals respectively.

9. 发明专利

DE69028617D1 未知
公开(公告)号：DE69028617D1
公开(公告)日：1996-10-24
申请号：DE69028617
申请日：1990-12-28
申请人： HITACHI LTD
发明人： WATANABE TAKAO , KIMURA KATSUTAKA , ITOH KIYOO , KAWAJIRI YOSHIKI
IPC分类号： G06F17/16 , G06N3/04 , G06F15/18 , G06N3/063 , G06N99/00 , G06F13/00 , G06F15/80
摘要： Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.

10. 发明专利

DE3688222D1 未知
公开(公告)号：DE3688222D1
公开(公告)日：1993-05-13
申请号：DE3688222
申请日：1986-07-10
申请人： HITACHI LTD
发明人： WATANABE TAKAO , KITUKAWA GORO , HORI RYOICHI , ITOH KIYOO , KAWAJIRI YOSHIKI , KAWAHARA TAKAYUKI
IPC分类号： G11C7/12 , G11C8/10 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/017 , H03K19/0175 , H03K19/0944 , H03K5/02 , H03K19/08 , H03K19/01 , H03K19/096 , G11C7/00
摘要： A semiconductor device of high integration density and low power consumption prevents the influence of the amplitude of an input signal upon the amplitude of an output signal in such a way that a preceding circuit (C) and a succeeding circuit (D) are endowed with different reference voltages.In an aspect of performance, the semiconductor device is constructed of a circuit which includes a bipolar transistor (26) and an insulated-gate field effect transistor (25, 27, 291, and which operates with reference to one or more voltages (B1), at least one of the reference voltages having a voltage value different from a reference operating voltage (VA) of a preceding circuit (CI which controls the above circuit.In another aspect of performance, first switching means is interposed between a first reference voltage and an input node of a driver circuit, and second switching means is interposed between an output of a preceding circuit and the input of the driver circuit, so that when an output signal of the preceding circuit is at a high level, the second switch is turned "on" while the first switch is turned "off" thereby to produce a still higher potential, and that when the output signal of the preceding circuit is at a low level, the second switch is turned "off" while the first switch is turned "on".The semiconductor device is suited to those circuits of a high-density DRAM and SRAM which use voltage limiters.

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