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1. 发明授权

US06750129B2 Process for forming fusible links 有权
标题翻译：形成易熔连接的工艺
公开(公告)号：US06750129B2
公开(公告)日：2004-06-15
申请号：US10292399
申请日：2002-11-12
申请人： Gwo-Shii Yang , Jen Kon Chen , Hsueh-Chung Chen , Hans-Joachim Barth , Chiung-Sheng Hsiung , Chih-Chien Liu , Tong-Yu Chen , Yi-hsiung Lin , Chih-Chao Yang
发明人： Gwo-Shii Yang , Jen Kon Chen , Hsueh-Chung Chen , Hans-Joachim Barth , Chiung-Sheng Hsiung , Chih-Chien Liu , Tong-Yu Chen , Yi-hsiung Lin , Chih-Chao Yang
IPC分类号： H01L213205
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.
摘要翻译：一种用于在集成电路中形成可熔链节的方法，其中可熔链在最终金属化层中与焊盘同时形成。该方法可以应用于采用铜金属化和低k电介质材料的集成电路的制造中。在对最终的金属（铝）层进行构图以形成可熔连接件和接合焊盘之后，在沉积钝化层之前，在最终的金属层上形成介电蚀刻停止层。钝化层在可熔接头和接合焊盘上的区域中被去除。电介质蚀刻停止层仅从接合焊盘上方或者从焊盘和可熔连接部上方移除。

2. 发明授权

US06890851B2 Interconnection structure and fabrication method thereof 有权
公开(公告)号：US06890851B2
公开(公告)日：2005-05-10
申请号：US10449262
申请日：2003-05-29
申请人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
发明人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76829 , H01L21/76801 , H01L21/76807
摘要： An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k dielectric layer. The opening is then filled with a conductive material to form an interconnection structure. The stress redistribution layer has a heat expansion coefficient closer to that of the substrate, while such heat expansion coefficient differs more significantly from those of the first and second organic low-k material layers.

3. 发明申请

US20050001321A1 Interconnection structure and fabrication method thereof 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US20050001321A1
公开(公告)日：2005-01-06
申请号：US10893632
申请日：2004-07-15
申请人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
发明人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76829 , H01L21/76801 , H01L21/76807
摘要： An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k dielectric layer. The opening is then filled with a conductive material to form an interconnection structure. The stress redistribution layer has a heat expansion coefficient closer to that of the substrate, while such heat expansion coefficient differs more significantly from those of the first and second organic low-k material layers.
摘要翻译：互连结构及其制造方法。在衬底上依次形成第一有机低k材料层，应力再分配层，第二有机低k电介质层，随后在第一有机低k材料层中形成开口，应力再分布层，和第二有机低k电介质层。然后用导电材料填充开口以形成互连结构。应力再分配层的热膨胀系数接近于基板的热膨胀系数，而这种热膨胀系数与第一和第二有机低k材料层的热膨胀系数的差异更显着。

4. 发明授权

US07179732B2 Interconnection structure and fabrication method thereof 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US07179732B2
公开(公告)日：2007-02-20
申请号：US10893632
申请日：2004-07-15
申请人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
发明人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/311
CPC分类号： H01L21/76829 , H01L21/76801 , H01L21/76807
摘要： An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k dielectric layer. The opening is then filled with a conductive material to form an interconnection structure. The stress redistribution layer has a heat expansion coefficient closer to that of the substrate, while such heat expansion coefficient differs more significantly from those of the first and second organic low-k material layers.
摘要翻译：互连结构及其制造方法。在衬底上依次形成第一有机低k材料层，应力再分配层，第二有机低k电介质层，随后在第一有机低k材料层中形成开口，应力再分布层，和第二有机低k电介质层。然后用导电材料填充开口以形成互连结构。应力再分配层的热膨胀系数接近于基板的热膨胀系数，而这种热膨胀系数与第一和第二有机低k材料层的热膨胀系数的差异更显着。

5. 发明申请

US20050101128A1 Method of patterning damascene structure in integrated circuit design 失效
标题翻译：集成电路设计中图案镶嵌结构的方法
公开(公告)号：US20050101128A1
公开(公告)日：2005-05-12
申请号：US10704022
申请日：2003-11-07
申请人： Frederick Gibb , Chih-Chao Yang , Yi-Hsiung Lin
发明人： Frederick Gibb , Chih-Chao Yang , Yi-Hsiung Lin
IPC分类号： H01L21/302 , H01L21/311 , H01L21/461 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/76831
摘要： Disclosed is a method that deposits an aqueous material having a pH between approximately 10 and 11 in a first opening and on an oxide hard mask, deposits an organic material on the aqueous material, and patterns a photoresist over the organic material. The invention then etches the organic material and the aqueous material through the photoresist to form a second opening above the first opening and forms a polymer along sidewalls of the second opening. The invention can then perform a wet cleaning process using an alkali solution having a pH between approximately 10 and 11 to remove the aqueous material from the first opening. By utilizing an alkali aqueous (water-based) material having a pH of approximately 10-11, the invention can use a fairly low pH wet etch (pH of approximately 10-11) to completely remove the aqueous solution from the via, thereby eliminating the conventional problem of having residual organic material left within the via.
摘要翻译：公开了一种在第一开口和氧化物硬掩模上沉积具有大约10和11之间的pH的水性材料的方法，将有机材料沉积在水性材料上，并在有机材料上形成光致抗蚀剂。然后，本发明通过光致抗蚀剂蚀刻有机材料和水性材料，以在第一开口上方形成第二开口，并沿着第二开口的侧壁形成聚合物。然后，本发明可以使用pH在约10和11之间的碱溶液进行湿式清洗，以从第一开口去除含水材料。通过使用pH为约10-11的碱性水性（水性）材料，本发明可以使用相当低的pH湿法蚀刻（约10-11的pH）从通孔中完全除去水溶液，从而消除在残留有机材料留在通孔内的常规问题。

6. 发明申请

US20050077628A1 Dual damascene structure and method 有权
公开(公告)号：US20050077628A1
公开(公告)日：2005-04-14
申请号：US10684952
申请日：2003-10-14
申请人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
发明人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

7. 发明授权

US07091612B2 Dual damascene structure and method 有权
公开(公告)号：US07091612B2
公开(公告)日：2006-08-15
申请号：US10684952
申请日：2003-10-14
申请人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas C. La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
发明人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas C. La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
IPC分类号： H01L23/12 , H01L23/48 , H01L23/52
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

8. 发明申请

US20080020327A1 METHOD OF FORMATION OF A DAMASCENE STRUCTURE 审中-公开
标题翻译：形成大分子结构的方法
公开(公告)号：US20080020327A1
公开(公告)日：2008-01-24
申请号：US11458499
申请日：2006-07-19
申请人： Chih-Chao Yang , Wai-Kin Li , Yi-Hsiung Lin
发明人： Chih-Chao Yang , Wai-Kin Li , Yi-Hsiung Lin
IPC分类号： G03F7/26
CPC分类号： H01L21/76808
摘要： A method in which during the formation of damascene features in a semiconductor structure, a planarization material is added to vias formed in the dielectric to protect the vias during subsequent lithographic processing. The planarization material preferred is a developable photosensitive material which can be exposed and developed to define the damascene features rather than etching as is conventional.
摘要翻译：一种在半导体结构中形成镶嵌特征的方法中，将平坦化材料添加到在电介质中形成的通孔中，以在随后的光刻处理期间保护通孔。优选的平坦化材料是可显影的感光材料，其可以暴露和显影以限定镶嵌特征，而不是如常规的蚀刻。

9. 发明授权

US06949459B2 Method of patterning damascene structure in integrated circuit design 失效
公开(公告)号：US06949459B2
公开(公告)日：2005-09-27
申请号：US10704022
申请日：2003-11-07
申请人： Wai-Kin Li , Chih-Chao Yang , Yi-hsiung Lin
发明人： Wai-Kin Li , Chih-Chao Yang , Yi-hsiung Lin
IPC分类号： H01L21/302 , H01L21/311 , H01L21/461 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/76831
摘要： Disclosed is a method that deposits an aqueous material having a pH between approximately 10 and 11 in a first opening and on an oxide hard mask, deposits an organic material on the aqueous material, and patterns a photoresist over the organic material. The invention then etches the organic material and the aqueous material through the photoresist to form a second opening above the first opening and forms a polymer along sidewalls of the second opening. The invention can then perform a wet cleaning process using an alkali solution having a pH between approximately 10 and 11 to remove the aqueous material from the first opening. By utilizing an alkali aqueous (water-based) material having a pH of approximately 10-11, the invention can use a fairly low pH wet etch (pH of approximately 10-11) to completely remove the aqueous solution from the via, thereby eliminating the conventional problem of having residual organic material left within the via.

10. 发明授权

US08957519B2 Structure and metallization process for advanced technology nodes 有权
标题翻译：先进技术节点的结构和金属化过程
公开(公告)号：US08957519B2
公开(公告)日：2015-02-17
申请号：US12910075
申请日：2010-10-22
申请人： Chih-Chao Yang , Hsueh-Chung Chen
发明人： Chih-Chao Yang , Hsueh-Chung Chen
IPC分类号： H01L23/48 , H01L21/321 , H01L21/02 , H01L21/768
CPC分类号： H01L21/321 , H01L21/02304 , H01L21/76852 , H01L21/76886
摘要： The problem of poor adherence of a dielectric coating on a patterned metal structure can be solved by forming an adhesion layer on exposed surfaces of such metal structure prior to deposition of such dielectric. According to an embodiment, the invention provides a method to form a self-aligned adhesion layer on the surface of metal interconnect structure within an integrated circuit by exposing the metal structure to a controlled atmosphere and a flow of nitrogen-containing gas.
摘要翻译：可以通过在沉积这种电介质之前在这种金属结构的暴露表面上形成粘合层来解决图案化金属结构上的电介质涂层粘附性差的问题。根据一个实施例，本发明提供了一种通过将金属结构暴露于受控气氛和含氮气体的流动来在集成电路内的金属互连结构的表面上形成自对准粘附层的方法。

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