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    • 2. 发明授权
    • Method and system for reliably defining and determining timeout values in unreliable datagrams
    • 用于在不可靠数据报中可靠地定义和确定超时值的方法和系统
    • US06748559B1
    • 2004-06-08
    • US09692349
    • 2000-10-19
    • Gregory Francis PfisterGiles Roger FrazierDanny Marvin NealSteven Mark Thurber
    • Gregory Francis PfisterGiles Roger FrazierDanny Marvin NealSteven Mark Thurber
    • G06F1100
    • H04L41/00H04L41/046H04L41/0806H04L41/082H04L41/12H04L43/0852
    • A method for managing allocation of network resources within the distributed computer system is provided. Specifically, the network traversal time and the end node response time for requests and/or packets being routed in a switch-connected system area network are utilized to determine the total round trip time for completion of the particular network operation. The sum of the timeout values for all switches that participate in routing the request from a requester (source) to the receptor node (target) is provided to the requester's channel adapter (CA). The time-out values are provided by the switch manufacturer and are sent to a network Subnet Manager (SM) via SM packets (SMP). The timeout values added together represent the SubnetTimeout. The time-out value of the target channel adapter (CA), the ResponseTime, is also provided to the requester. The requester then utilizes one of two timeout equations to calculate the overall response time required for the request to be completed. A timer is started and the elapsed time to complete the request is monitored and compared with the overall response time calculated. When the timer expires before a response is received at the requester, the operation is assumed to have failed and the network resources being utilized by the request may be reallocated to another network operation.
    • 提供了一种管理分布式计算机系统内网络资源分配的方法。 具体地,利用在交换机连接的系统区域网络中路由的请求和/或分组的网络遍历时间和终止节点响应时间来确定完成特定网络操作的总往返时间。 参与将请求从请求者(源)路由到接收节点(目标)的所有交换机的超时值的总和提供给请求者的信道适配器(CA)。 超时值由交换机制造商提供,并通过SM数据包(SMP)发送到网络子网管理器(SM)。 添加的超时值表示SubnetTimeout。 目标通道适配器(CA)的超时值ResponseTime也提供给请求者。 然后,请求者使用两个超时方程之一来计算请求完成所需的总体响应时间。 启动定时器,并监视完成请求的经过时间,并与计算的总响应时间进行比较。 当定时器在请求者接收到响应之前到期时,假设该操作已经失败,并且该请求所利用的网络资源可能被重新分配到另一个网络操作。
    • 3. 发明授权
    • Method and apparatus for reliably choosing a master network manager during initialization of a network computing system
    • 在网络计算系统的初始化期间可靠地选择主网络管理器的方法和装置
    • US06941350B1
    • 2005-09-06
    • US09692346
    • 2000-10-19
    • Giles Roger FrazierGregory Francis PfisterSteven Mark ThurberDono Van-Mierop
    • Giles Roger FrazierGregory Francis PfisterSteven Mark ThurberDono Van-Mierop
    • G06F15/16G06F15/173
    • G06F15/17375H04L63/061
    • A method in a node within network computing system for selecting a master network manager, wherein the first node is associated with a first priority. Requests are sent to the network computing system to discover other nodes within the network computing system. A second priority from the request is identified in response to receiving a response to one of the requests from another node within the network computing system. The first node shifts to a standby mode if it discovers a master subnet manager or the second priority is higher than the first priority. The first node shifts to a master mode if a response containing a priority higher than the first priority is absent in responses received by the first node and the first node has completed checking all other nodes in the network computing system. In the case where the priority received is equal, the comparison is further made on the globally unique identifier which is received from the same node, in which case the node with the lowest globally unique identifier wins the arbitration.
    • 网络计算系统内用于选择主网络管理器的节点中的方法,其中所述第一节点与第一优先级相关联。 将请求发送到网络计算系统以发现网络计算系统内的其他节点。 响应于响应于来自网络计算系统内的另一个节点的一个请求的响应来识别来自请求的第二优先级。 如果发现主子网管理器或第二优先级高于第一优先级,则第一节点转移到待机模式。 如果在由第一节点接收的响应中缺少包含高于第一优先级的优先级的响应,则第一节点转移到主模式,并且第一节点已经完成了对网络计算系统中的所有其他节点的检查。 在接收到的优先级相等的情况下,进一步对从同一节点接收到的全局唯一标识符进行比较,在这种情况下,具有最低全局唯一标识符的节点赢得仲裁。
    • 5. 发明授权
    • Method and system for choosing a queue protection key that is tamper-proof from an application
    • 从应用程序中选择防篡改的队列保护密钥的方法和系统
    • US06851059B1
    • 2005-02-01
    • US09692353
    • 2000-10-19
    • Gregory Francis PfisterRenato John RecioDanny Marvin NealSteven Mark Thurber
    • Gregory Francis PfisterRenato John RecioDanny Marvin NealSteven Mark Thurber
    • H04L9/00H04L29/06
    • H04L63/06
    • A method for enabling a Q_key that is tamper proof from applications on a distributed computer system to protect selected network operations is provided. Applications and an operating system (OS) execute on the end nodes and each may access various network resources. In the invention, the network resources are configured for selective access by particular applications or OS.In a preferred embodiment, a control bit of a Q_key, which allows applications to authenticate their use of particular communication resources, i.e., the send and receive queues, is reserved and utilized to signal whether a particular application is allowed access to the resources. Setting the control bit to 0 allows the Q_key to be set by an application directly. When the control bit is set to 1, the Q_key cannot be set by an application and can only be set using a privileged operation performed only by the OS.
    • 提供了一种用于启用防止来自分布式计算机系统上的应用程序的防篡改的Q_key以保护所选网络操作的方法。 应用和操作系统(OS)在终端节点上执行,每个可以访问各种网络资源。 在本发明中,网络资源被配置用于特定应用或OS的选择性访问。在优选实施例中,Q_key的控制位允许应用程序认证其对特定通信资源的使用,即发送和接收队列, 被保留并用于发出特定应用是否被允许访问资源。 将控制位设置为0允许应用程序直接设置Q_key。 当控制位设置为1时,Q_key不能由应用程序设置,只能使用仅由操作系统执行的特权操作进行设置。
    • 8. 发明授权
    • Associating buffers in a bus bridge with corresponding peripheral devices to facilitate transaction merging
    • 将总线桥中的缓冲区与对应的外围设备相关联,以便于事务合并
    • US06324612B1
    • 2001-11-27
    • US09210133
    • 1998-12-10
    • Wen-Tzer Thomas ChenRichard A. KelleyDanny Marvin NealSteven Mark Thurber
    • Wen-Tzer Thomas ChenRichard A. KelleyDanny Marvin NealSteven Mark Thurber
    • G06F1340
    • G06F13/4059G06F13/4031
    • A bus bridge including a buffer pool and steering logic where the buffer pool is organized as a plurality of buffers sets including at least first and second buffer sets and the steering logic is adapted to store transactions originating with a first peripheral device in the first buffer set and transactions originating with a second peripheral device in the second buffer set. Transactions may arrive via a secondary bus, such as a PCI bus, coupled to the bus bridge. The bridge further allows relaxed transaction ordering rules compared to conventional PCI transaction ordering rules by identifying transactions by grant signals and thus allows steering of transactions from the first and second devices to first and second buffer sets respectively. The bridge is suitably adapted for combining or merging two or more transactions within each buffer set. Each buffer set preferably includes one or more buffers for temporarily storing transactions arriving from the secondary bus and bound for a primary bus. The primary bus may comprise a host bus connected to one or more processors or an additional PCI bus or other peripheral bus. The invention further contemplates a computer system including at least one processor, a bridge coupled to the processor via a host bus, and a plurality of peripheral devices including first and second peripheral devices coupled to the bridge via a secondary bus. In one embodiment, the bridge is configured to receive first and second request signals from the first and second peripheral devices respectively. The bridge preferably further includes arbitration logic for arbitrating mastership of the secondary bus in response to the request signals to produce first and second grant signals. The steering logic is suitably configured to utilize the first and second grant signals to determine the source of a subsequent transaction.
    • 一种包括缓冲池和转向逻辑的总线桥,其中所述缓冲池被组织为包括至少第一和第二缓冲器组的多个缓冲器组,并且所述转向逻辑适于将始发于第一外围设备的事务存储在所述第一缓冲器组中 以及在第二缓冲器组中产生具有第二外围设备的交易。 事务可以通过耦合到总线桥的辅助总线(诸如PCI总线)到达。 与传统PCI事务排序规则相比,通过由授权信号识别事务并且因此允许将事务从第一和第二设备分别转向第一和第二缓冲器组,桥还允许轻松的事务排序规则。 该桥适用于组合或合并每个缓冲区内的两个或多个事务。 每个缓冲器组优选地包括一个或多个缓冲器,用于临时存储从次级总线到达并且被绑定到主总线的事务。 主总线可以包括连接到一个或多个处理器或附加PCI总线或其他外围总线的主机总线。 本发明进一步考虑了一种包括至少一个处理器,经由主机总线耦合到处理器的桥的计算机系统,以及包括通过次级总线耦合到桥接器的第一和第二外围设备的多个外围设备。 在一个实施例中,桥被配置为分别从第一和第二外围设备接收第一和第二请求信号。 桥接器优选地还包括用于响应于请求信号来仲裁辅助总线的主管以产生第一和第二授权信号的仲裁逻辑。 转向逻辑被适当地配置为利用第一和第二授权信号来确定后续交易的来源。
    • 9. 发明授权
    • Interrupt response in a multiple set buffer pool bus bridge
    • 多组缓冲池总线桥中的中断响应
    • US06301630B1
    • 2001-10-09
    • US09210127
    • 1998-12-10
    • Wen-Tzer Thomas ChenRichard A. KelleyDanny Marvin NealSteven Mark Thurber
    • Wen-Tzer Thomas ChenRichard A. KelleyDanny Marvin NealSteven Mark Thurber
    • G06F1300
    • G06F13/4059
    • A bus bridge including a buffer pool comprised of a first and a second buffer sets. The first and second buffer sets are associated with first and second peripheral devices respectively. The bridge is configured to receive an interrupt and identify the interrupt source. A buffer set associated with the interrupt source is selected and transactions in the selected buffer set flushed prior to forwarding the interrupt to a processor. The bridge is preferably configured to identify the interrupt source by receiving a first interrupt signal from the first peripheral device and a second interrupt signal from the second peripheral device. Preferably, the bridge is configured to flush the transactions by pushing them into system memory via a primary bus such as a host bus of a processor. The invention further contemplates a system including a processor coupled to a host bus, a system memory, a bus bridge as described coupled between the host bus and a secondary bus, and first and second peripheral devices coupled to the secondary bus. Upon receiving an interrupt, the bridge is configured to identify the interrupt source, select a buffer set associated with the interrupt source, and flush posted memory write transactions in the selected buffer set, all prior to forwarding the interrupt to the processor. In one embodiment, the bridge, the first and second peripheral devices, and the secondary bus are compliant with the PCI specification. The bridge is configured in one embodiment to receive unique first and second interrupt signals from the first and second peripheral devices respectively.
    • 包括由第一和第二缓冲器组构成的缓冲池的总线桥。 第一和第二缓冲器组分别与第一和第二外围设备相关联。 桥接器配置为接收中断并识别中断源。 选择与中断源关联的缓冲区,并将所选缓冲区中的事务刷新,然后再将中断转发给处理器。 优选地,桥被配置为通过从第一外围设备接收第一中断信号和来自第二外围设备的第二中断信号来识别中断源。 优选地,桥被配置为通过经由诸如处理器的主机总线的主总线将其推入系统存储器来刷新事务。 本发明进一步考虑了一种系统,其包括耦合到主机总线的处理器,系统存储器,耦合在主机总线和辅助总线之间的总线桥,以及耦合到次级总线的第一和第二外围设备。 在接收到中断时,桥被配置为识别中断源,选择与中断源相关联的缓冲区集合,以及在将中断转发到处理器之前清除所选缓冲区中的已发布的存储器写入事务。 在一个实施例中,桥接器,第一和第二外围器件以及辅助总线符合PCI规范。 在一个实施例中,桥被配置为分别从第一和第二外围设备接收唯一的第一和第二中断信号。
    • 10. 发明授权
    • Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across a PCI host bridge supporting multiple PCI buses
    • 支持通过支持多个PCI总线的PCI主机桥的外围组件互连(PCI)对等访问的方法和系统
    • US06182178B2
    • 2001-01-30
    • US09106953
    • 1998-06-30
    • Richard Allen KelleyDanny Marvin NealSteven Mark Thurber
    • Richard Allen KelleyDanny Marvin NealSteven Mark Thurber
    • G06F1338
    • G06F13/4045
    • A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. First and second PCI local buses are connected to the system bus through a PCI host bridge. The first and second PCI local buses have sets of in-line electronic switches, dividing the PCI local buses into PCI local bus segments supporting a plurality of PCI peripheral component slots for connecting PCI devices. The sets of in-line electronic switches are open and closed in accordance with bus control logic within the PCI host bridge allowing up to fourteen or more PCI peripheral component slots for connecting up to fourteen PCI devices to have access through a single PCI host bridge to the system bus. An internal PCI-to-PCI bridge is provided to allow a PCI device to share data with another PCI device as peer-to-peer devices across the first and second PCI local bus segments.
    • 公开了一种通过在数据处理系统内具有多个PCI接口的单个​​PCI主机桥来支持多个外围组件互连(PCI)局部总线的方法和系统。 根据本发明的方法和系统,处理器和系统存储器连接到系统总线。 第一和第二PCI本地总线通过PCI主机桥连接到系统总线。 第一和第二PCI本地总线具有一组在线电子开关,将PCI本地总线划分成支持用于连接PCI设备的多个PCI外围组件插槽的PCI本地总线段。 根据PCI主机桥中的总线控制逻辑,这些在线电子开关是打开和关闭的,允许多达十四个或更多个PCI外设组件插槽,用于连接多达十四个PCI设备,以通过单个PCI主机桥访问 系统总线。 提供内部PCI至PCI桥接器,以允许PCI设备与第一和第二PCI本地总线段之间的对等设备与另一PCI设备共享数据。