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1. 发明授权

US06362762B1 Multiple mode analog-to-digital converter employing a single quantizer 有权
标题翻译：采用单个量化器的多模式模数转换器
公开(公告)号：US06362762B1
公开(公告)日：2002-03-26
申请号：US09645072
申请日：2000-08-23
申请人： Henrik T. Jensen , Gopal Raghavan
发明人： Henrik T. Jensen , Gopal Raghavan
IPC分类号： H03M300
CPC分类号： H03M3/396 , H03M3/428 , H03M3/448 , H03M3/454
摘要： Several delta-sigma modulator circuits and a single quantizer provide analog-to-digital conversion for multiple frequency bands. A wideband mode is provided by coupling an analog signal to be digitized directly to a quantizer. Narrowband modes are provided by switching the analog signal to be digitized into one of several delta-sigma modulator circuits. Noise shaping and filtering by the delta-sigma modulator circuits result in improved signal-to-noise-and-distortion performance and increased resolution. Performance is further enhanced by feeding back multiple bits output by the quantizer to the delta-sigma modulator circuits. The delta-sigma modulator circuits can be either continuous time or discrete time delta sigma modulators.
摘要翻译：几个Δ-Σ调制器电路和单个量化器为多个频带提供模数转换。通过将要直接数字化的模拟信号耦合到量化器来提供宽带模式。通过将要数字化的模拟信号切换成几个Δ-Σ调制器电路之一来提供窄带模式。由Δ-Σ调制器电路进行的噪声整形和滤波导致改善的信噪比和失真性能并提高分辨率。通过将由量化器输出的多个比特反馈到Δ-Σ调制器电路，进一步增强了性能。 Δ-Σ调制器电路可以是连续时间或离散时间ΔΣ调制器。

2. 发明授权

US06441759B1 Multi-bit &Dgr;&Sgr; modulator having linear output 有权
标题翻译：具有线性输出的多位DELTASIGMA调制器
公开(公告)号：US06441759B1
公开(公告)日：2002-08-27
申请号：US09651744
申请日：2000-08-30
申请人： Gopal Raghavan , Henrik T. Jensen
发明人： Gopal Raghavan , Henrik T. Jensen
IPC分类号： H03M300
CPC分类号： H03M3/428 , H03M3/436
摘要： An apparatus and method of improving linearity of a multi bit &Dgr;&Sgr; modulator in which the output of a multi-bit quantizer of a &Dgr;&Sgr; modulator is connected in a feedback loop to a converter where output is a higher frequency single bit data stream which is supplied to a 1-bit digital to analog converter whose output is fed back to the quantizer to provide linearity of the output of the &Dgr;&Sgr; modulator.
摘要翻译：一种提高多位DELTASIGMA调制器的线性度的装置和方法，其中DELTASIGMA调制器的多位量化器的输出在反馈环路中连接到转换器，其中输出是较高频率的单位数据流，其被提供给 1位数模转换器，其输出反馈给量化器，以提供DELTASIGMA调制器输出的线性。

3. 发明授权

US07307863B2 Programmable strength output buffer for RDIMM address register 有权
公开(公告)号：US07307863B2
公开(公告)日：2007-12-11
申请号：US11195910
申请日：2005-08-02
申请人： Jeffrey C. Yen , Nikhil K. Srivastava , Gopal Raghavan
发明人： Jeffrey C. Yen , Nikhil K. Srivastava , Gopal Raghavan
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C5/04 , G11C29/022 , G11C29/028
摘要： A programmable strength output buffer intended for use within the address register of a memory module such as a registered DIMM (RDIMM). The output signals of an array of such buffers drive respective output lines that are connected to the address or control pins of several RAM chips. The programmable buffers vary the strength of at least some of the output signals in response to a configuration control signal, such that the output signals can be optimized for the loads to which they will be connected.

4. 发明申请

US20070216445A1 Output buffer with switchable output impedance 有权
标题翻译：输出缓冲器，具有可切换的输出阻抗
公开(公告)号：US20070216445A1
公开(公告)日：2007-09-20
申请号：US11376593
申请日：2006-03-14
申请人： Gopal Raghavan , Dhruv Jain
发明人： Gopal Raghavan , Dhruv Jain
IPC分类号： H03K19/094
CPC分类号： H03K19/0005 , H03K19/018557 , H03K19/094
摘要： An output buffer with a switchable output impedance designed for driving a terminated signal line. The buffer includes a drive circuit, and a means for switching the output impedance of the drive circuit between a first, relatively low output impedance when the output buffer is operated in a ‘normal’ mode, and a second output impedance which is greater than the first output impedance when operated in a ‘standby’ mode. By increasing the drive circuit's output impedance while in ‘standby’ mode, power dissipation due to the termination resistor is reduced. When used in a memory system, additional power savings may be realized by arranging the buffer such that the increased impedance in ‘standby’ mode shifts the signal line voltage so as to avoid the voltage range over which a line receiver's power consumption is greatest.
摘要翻译：具有可切换输出阻抗的输出缓冲器，用于驱动端接的信号线。缓冲器包括驱动电路和用于在输出缓冲器以“正常”模式操作时将驱动电路的输出阻抗切换到第一相对低输出阻抗的装置，以及大于第二输出阻抗的第二输出阻抗在“待机”模式下运行时的第一个输出阻抗。通过在“待机”模式下增加驱动电路的输出阻抗，减少了由终端电阻引起的功耗。当用于存储器系统时，可以通过布置缓冲器来实现额外的功率节省，使得“待机”模式中的增加的阻抗使信号线电压移位，以避免线路接收机的功耗最大的电压范围。

5. 发明授权

US09423866B2 Asynchronous processor that adjusts a respective operating voltage for causing a task to consume substantially all of a respective allocated time interval for the task 有权
标题翻译：调整相应工作电压以使任务基本上消耗所有任务分配的时间间隔的异步处理器
公开(公告)号：US09423866B2
公开(公告)日：2016-08-23
申请号：US14801010
申请日：2015-07-16
申请人： Gopal Raghavan
发明人： Gopal Raghavan
IPC分类号： G06F1/26 , G06F1/32 , G06F1/00
CPC分类号： G06F1/3296 , G06F1/3203 , G06F1/3228 , G06F1/324 , G06F1/329 , G06F9/4893
摘要： There are disclosed asynchronous computing devices and methods of operating asynchronous computing devices. An asynchronous computing device may include an asynchronous processor and a voltage regulator circuit that outputs an operating voltage to the asynchronous processor in response to a voltage request received from the asynchronous processor.
摘要翻译：公开了异步计算设备和操作异步计算设备的方法。异步计算设备可以包括异步处理器和电压调节器电路，其响应于从异步处理器接收到的电压请求而将工作电压输出到异步处理器。

6. 发明申请

US20160018869A1 ASYNCHRONOUS PROCESSOR 有权
标题翻译：异步处理器
公开(公告)号：US20160018869A1
公开(公告)日：2016-01-21
申请号：US14801010
申请日：2015-07-16
申请人： Gopal Raghavan
发明人： Gopal Raghavan
IPC分类号： G06F1/32 , G06F9/48
CPC分类号： G06F1/3296 , G06F1/3203 , G06F1/3228 , G06F1/324 , G06F1/329 , G06F9/4893
摘要： There are disclosed asynchronous computing devices and methods of operating asynchronous computing devices. An asynchronous computing device may include an asynchronous processor and a voltage regulator circuit that outputs an operating voltage to the asynchronous processor in response to a voltage request received from the asynchronous processor.
摘要翻译：公开了异步计算设备和操作异步计算设备的方法。异步计算设备可以包括异步处理器和电压调节器电路，其响应于从异步处理器接收到的电压请求而将工作电压输出到异步处理器。

7. 发明授权

US08275936B1 Load reduction system and method for DIMM-based memory systems 有权
标题翻译：基于DIMM的内存系统的减负系统和方法
公开(公告)号：US08275936B1
公开(公告)日：2012-09-25
申请号：US12563308
申请日：2009-09-21
申请人： Christopher Haywood , Gopal Raghavan , Chao Xu
发明人： Christopher Haywood , Gopal Raghavan , Chao Xu
IPC分类号： G06F12/00
CPC分类号： G06F13/1657
摘要： A load reduction system and method for use with memory systems which include one or more DIMMs, each of which includes a circuit arranged to buffer data bytes being written to or read from the DIMM, with the system nominally organized such that the bytes of a given data word are conveyed to the DIMMs via respective byte lanes and stored in a given rank on a given DIMM. The system is arranged such that the DRAMs that constitute a given rank are re-mapped across the available DIMMs plugged into the slots, such that a data word to be stored in a given rank is striped across the available DIMMs, thereby reducing the loading on a given byte lane that might otherwise be present. The system is preferably arranged such that any given byte lane is wired to no more than two of the DIMM slots.
摘要翻译：一种用于与包括一个或多个DIMM的存储器系统一起使用的存储器系统的负载减小系统和方法，每个DIMM包括被配置为缓冲正在写入或从DIMM读取的数据字节的电路，其中系统被标称组织，使得给定的数据字通过相应的字节通道传送到DIMM，并以给定的DIMM上的给定等级存储。该系统被布置成使得构成给定等级的DRAM被重新映射到插入到插槽中的可用DIMM上，使得要存储在给定等级中的数据字在可用DIMM上条带化，从而减少了对否则可能存在的给定字节通道。该系统优选地布置成使得任何给定的字节通道被布线到不超过两个DIMM插槽。

8. 发明授权

US07408393B1 Master-slave flip-flop and clocking scheme 有权
标题翻译：主从触发器和时钟方案
公开(公告)号：US07408393B1
公开(公告)日：2008-08-05
申请号：US11716079
申请日：2007-03-08
申请人： Dhruv Jain , Gopal Raghavan , Jeffrey C. Yen , Carl W. Pobanz
发明人： Dhruv Jain , Gopal Raghavan , Jeffrey C. Yen , Carl W. Pobanz
IPC分类号： H03K3/289
CPC分类号： H03K3/0372 , H03K3/35625 , H03K5/133 , H03K5/135
摘要： A master-slave flip-flop comprises master and slave latches, with the data output of the master latch connected to the data input of the slave latch. The latches receive clock signals CKM and CKS at their respective clock inputs; each latch is transparent when its clock signal is in a first state and latches a signal applied to its input when its clock signal is in a second state. A clock buffer receives an input clock CKin and generates nominally complementary clock signals CKM and CKS such that one latch is latched while the other is transparent. The clock buffer is arranged to skew CKS with respect to CKM such that the slave latch is made transparent earlier than it would without the skew, making the minimum delay (tpd) between the toggling of CKin and a resulting change at the slave latch's output less than it would otherwise be.
摘要翻译：主从触发器包括主锁存器和从锁存器，主锁存器的数据输出连接到从锁存器的数据输入。锁存器在其各自的时钟输入端接收时钟信号CKM和CKS; 当其时钟信号处于第一状态时，每个锁存器是透明的，并且当其时钟信号处于第二状态时锁存施加到其输入端的信号。时钟缓冲器接收中的输入时钟CK，并产生标称互补的时钟信号CKM和CKS，使得一个锁存器被锁存，而另一个锁存器是透明的。时钟缓冲器被布置成相对于CKM偏斜CKS，使得从锁存器比不存在偏斜更早地变得透明，从而在CK pd ） >在中，从属锁存器输出的结果变化小于否则将会减少。

9. 发明申请

US20050077992A1 Symmetric planar inductor 审中-公开
标题翻译：对称平面电感
公开(公告)号：US20050077992A1
公开(公告)日：2005-04-14
申请号：US10666532
申请日：2003-09-19
申请人： Gopal Raghavan , Michael Case
发明人： Gopal Raghavan , Michael Case
IPC分类号： H01F17/00 , H01F27/34 , H01L23/522 , H01F5/00
CPC分类号： H01L23/5227 , H01F17/0006 , H01F27/34 , H01F2017/0046 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A substantially symmetric inductor comprising a plurality of windings, at least one conductor crossover, and a peripheral conductor disposed at the periphery of the plurality of windings, the plurality of windings having a generally symmetric shape, each of the plurality of windings having a center and being of a different size from other ones of the plurality of windings, the peripheral conductor being generally symmetric and having a center, the plurality of windings and the peripheral conductor being substantially concentric, the conductor crossovers being disposed such that the symmetry of the inductor in substantially preserved. A method of winding an inductor such that the inductor is substantially symmetric about a center of the inductor, whereby signal degradation due to asymmetry of the inductor is substantially minimized.
摘要翻译：一种基本对称的电感器，包括多个绕组，至少一个导体交叉和设置在所述多个绕组的外围的周边导体，所述多个绕组具有大致对称的形状，所述多个绕组中的每一个具有中心和与多个绕组中的其它绕组具有不同的尺寸，外围导体大致对称并具有中心，多个绕组和外围导体基本上是同心的，导体跨接器被布置成使得电感器的对称性基本保存。绕组电感器的方法使得电感器基本上对称于电感器的中心，由此由于电感器的不对称引起的信号劣化基本上被最小化。

10. 发明授权

US06621331B2 Variable negative resistance cell for bipolar integrated circuits 失效
标题翻译：双极集成电路的可变负电阻电池
公开(公告)号：US06621331B2
公开(公告)日：2003-09-16
申请号：US09925828
申请日：2001-08-07
申请人： Carl W. Pobanz , Gopal Raghavan
发明人： Carl W. Pobanz , Gopal Raghavan
IPC分类号： H03K300
CPC分类号： H03B27/00 , H03B5/1212 , H03B5/1231 , H03B5/1287 , H03B2201/036
摘要： An effective means and apparatus for generating a negative resistance including a circuit element that exhibits an increase in current as the applied voltage is decreased. Other embodiments of the present invention provide electronic means for improving the quality Q factor of on-chip resonators, which enables the creation of high-performance bipolar RF circuits with a minimum of external components.
摘要翻译：一种用于产生负电阻的有效装置和装置，包括随施加电压而呈现电流增加的电路元件。本发明的其他实施例提供用于改善片上谐振器的质量Q因子的电子装置，其使得能够利用最少的外部部件创建高性能双极性RF电路。

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