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1. 发明授权

US07408393B1 Master-slave flip-flop and clocking scheme 有权
标题翻译：主从触发器和时钟方案
公开(公告)号：US07408393B1
公开(公告)日：2008-08-05
申请号：US11716079
申请日：2007-03-08
申请人： Dhruv Jain , Gopal Raghavan , Jeffrey C. Yen , Carl W. Pobanz
发明人： Dhruv Jain , Gopal Raghavan , Jeffrey C. Yen , Carl W. Pobanz
IPC分类号： H03K3/289
CPC分类号： H03K3/0372 , H03K3/35625 , H03K5/133 , H03K5/135
摘要： A master-slave flip-flop comprises master and slave latches, with the data output of the master latch connected to the data input of the slave latch. The latches receive clock signals CKM and CKS at their respective clock inputs; each latch is transparent when its clock signal is in a first state and latches a signal applied to its input when its clock signal is in a second state. A clock buffer receives an input clock CKin and generates nominally complementary clock signals CKM and CKS such that one latch is latched while the other is transparent. The clock buffer is arranged to skew CKS with respect to CKM such that the slave latch is made transparent earlier than it would without the skew, making the minimum delay (tpd) between the toggling of CKin and a resulting change at the slave latch's output less than it would otherwise be.
摘要翻译：主从触发器包括主锁存器和从锁存器，主锁存器的数据输出连接到从锁存器的数据输入。锁存器在其各自的时钟输入端接收时钟信号CKM和CKS; 当其时钟信号处于第一状态时，每个锁存器是透明的，并且当其时钟信号处于第二状态时锁存施加到其输入端的信号。时钟缓冲器接收中的输入时钟CK，并产生标称互补的时钟信号CKM和CKS，使得一个锁存器被锁存，而另一个锁存器是透明的。时钟缓冲器被布置成相对于CKM偏斜CKS，使得从锁存器比不存在偏斜更早地变得透明，从而在CK pd ） >在中，从属锁存器输出的结果变化小于否则将会减少。

2. 发明授权

US07307863B2 Programmable strength output buffer for RDIMM address register 有权
公开(公告)号：US07307863B2
公开(公告)日：2007-12-11
申请号：US11195910
申请日：2005-08-02
申请人： Jeffrey C. Yen , Nikhil K. Srivastava , Gopal Raghavan
发明人： Jeffrey C. Yen , Nikhil K. Srivastava , Gopal Raghavan
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C5/04 , G11C29/022 , G11C29/028
摘要： A programmable strength output buffer intended for use within the address register of a memory module such as a registered DIMM (RDIMM). The output signals of an array of such buffers drive respective output lines that are connected to the address or control pins of several RAM chips. The programmable buffers vary the strength of at least some of the output signals in response to a configuration control signal, such that the output signals can be optimized for the loads to which they will be connected.

3. 发明授权

US07551651B1 Method and system for time domain multiplexers with reduced inter-symbol interference 有权
标题翻译：减少符号间干扰的时域多路复用器的方法和系统
公开(公告)号：US07551651B1
公开(公告)日：2009-06-23
申请号：US10352740
申请日：2003-01-27
申请人： Jeffrey C. Yen
发明人： Jeffrey C. Yen
IPC分类号： H04J3/02
CPC分类号： H04J3/10 , H04J3/047
摘要： Method and system for a high-speed multiplexer with reduced inter-symbol interference are disclosed. In one embodiment of the present invention, two input bit streams are interleaved by a multiplexer to derive an output bit stream. Each input bit stream is latched by a return-to-differential-zero latch that drives its input bit stream to a neutral state when it is not selected by the multiplexer as output. In an alternate embodiment of the present invention, a pre-selector receives two input signals, determines which of the two input signals will be selected as output of the multiplexer and passes the bit stream unaltered, while passing a differential zero value in place of the unselected input bit stream.
摘要翻译：公开了一种减少符号间干扰的高速多路复用器的方法和系统。在本发明的一个实施例中，两个输入比特流由多路复用器进行交织以导出输出比特流。每个输入比特流由返回 - 差分零锁存器锁存，当不被多路复用器输出时，其将其输入比特流驱动到空闲状态。在本发明的替代实施例中，预选器接收两个输入信号，确定两个输入信号中的哪一个将被选择为多路复用器的输出，并且通过位流不改变，同时通过差分零值代替未选择的输入位流。

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