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1. 发明授权

US08275936B1 Load reduction system and method for DIMM-based memory systems 有权
标题翻译：基于DIMM的内存系统的减负系统和方法
公开(公告)号：US08275936B1
公开(公告)日：2012-09-25
申请号：US12563308
申请日：2009-09-21
申请人： Christopher Haywood , Gopal Raghavan , Chao Xu
发明人： Christopher Haywood , Gopal Raghavan , Chao Xu
IPC分类号： G06F12/00
CPC分类号： G06F13/1657
摘要： A load reduction system and method for use with memory systems which include one or more DIMMs, each of which includes a circuit arranged to buffer data bytes being written to or read from the DIMM, with the system nominally organized such that the bytes of a given data word are conveyed to the DIMMs via respective byte lanes and stored in a given rank on a given DIMM. The system is arranged such that the DRAMs that constitute a given rank are re-mapped across the available DIMMs plugged into the slots, such that a data word to be stored in a given rank is striped across the available DIMMs, thereby reducing the loading on a given byte lane that might otherwise be present. The system is preferably arranged such that any given byte lane is wired to no more than two of the DIMM slots.
摘要翻译：一种用于与包括一个或多个DIMM的存储器系统一起使用的存储器系统的负载减小系统和方法，每个DIMM包括被配置为缓冲正在写入或从DIMM读取的数据字节的电路，其中系统被标称组织，使得给定的数据字通过相应的字节通道传送到DIMM，并以给定的DIMM上的给定等级存储。该系统被布置成使得构成给定等级的DRAM被重新映射到插入到插槽中的可用DIMM上，使得要存储在给定等级中的数据字在可用DIMM上条带化，从而减少了对否则可能存在的给定字节通道。该系统优选地布置成使得任何给定的字节通道被布线到不超过两个DIMM插槽。

2. 发明授权

US08898368B2 Redriven/retimed registered dual inline memory module 有权
标题翻译：重新配置/重新定时注册的双列直插式内存模块
公开(公告)号：US08898368B2
公开(公告)日：2014-11-25
申请号：US12267355
申请日：2008-11-07
申请人： Christopher Haywood , Gopal Raghavan
发明人： Christopher Haywood , Gopal Raghavan
IPC分类号： G06F13/00 , G11C5/04 , G06F13/16 , G06F13/40
CPC分类号： G11C5/04 , G06F13/1694 , G06F13/4072
摘要： A memory module may include a plurality of dynamic random access memory (DRAM) chips, each of which may have one or more data input/output (D/Q) terminals. The memory module may include data redriving/retiming circuits connected to the D/Q terminals of the plurality of DRAM chips. The data redriving/retiming circuits may provide isolation between a system memory bus and the D/Q terminals of the DRAM chips.
摘要翻译：存储器模块可以包括多个动态随机存取存储器（DRAM）芯片，每个芯片可以具有一个或多个数据输入/输出（D / Q）端子。存储器模块可以包括连接到多个DRAM芯片的D / Q端子的数据重传/重新定时电路。数据恢复/重新定时电路可以提供系统存储器总线与DRAM芯片的D / Q端子之间的隔离。

3. 发明申请

US20090119451A1 Redriven/Retimed Registered Dual Inline Memory Module 有权
标题翻译：重新注册/重新定时注册双列直插内存模块
公开(公告)号：US20090119451A1
公开(公告)日：2009-05-07
申请号：US12267355
申请日：2008-11-07
申请人： Christopher Haywood , Gopal Raghavan
发明人： Christopher Haywood , Gopal Raghavan
IPC分类号： G06F12/02
CPC分类号： G11C5/04 , G06F13/1694 , G06F13/4072
摘要： A memory module may include a plurality of dynamic random access memory (DRAM) chips, each of which may have one or more data input/output (D/Q) terminals. The memory module may include data redriving/retiming circuits connected to the D/Q terminals of the plurality of DRAM chips. The data redriving/retiming circuits may provide isolation between a system memory bus and the D/Q terminals of the DRAM chips.
摘要翻译：存储器模块可以包括多个动态随机存取存储器（DRAM）芯片，每个芯片可以具有一个或多个数据输入/输出（D / Q）端子。存储器模块可以包括连接到多个DRAM芯片的D / Q端子的数据重传/重新定时电路。数据恢复/重新定时电路可以提供系统存储器总线与DRAM芯片的D / Q端子之间的隔离。

4. 发明授权

US07012896B1 Dedicated bandwidth data communication switch backplane 失效
公开(公告)号：US07012896B1
公开(公告)日：2006-03-14
申请号：US09154966
申请日：1998-09-17
申请人： Christopher Haywood , Geoffrey C. Stone
发明人： Christopher Haywood , Geoffrey C. Stone
IPC分类号： H04L12/26 , H04L12/28
CPC分类号： H04L49/351 , H04L12/4641 , H04L45/7453 , H04L49/354
摘要： A LAN switch has a backplane matrix in which each controller has a dedicated packet bus for propagating packet data. Each bus has a root interfacing with the transmitting (root) controller and a plurality of leaves interfacing with receiving (leaf) controllers. This configuration enables each controller to simultaneously transmit packet data on the root of a bus and receive packet data off a plurality of leaves of other buses without contention. An efficient filtering and stalling system employed at the receive side of the backplane prevents the highly parallel traffic from causing receive side congestion.

5. 发明授权

US08880790B2 Methods and apparatus for transferring data between memory modules 有权
标题翻译：用于在内存模块之间传输数据的方法和装置
公开(公告)号：US08880790B2
公开(公告)日：2014-11-04
申请号：US13619692
申请日：2012-09-14
申请人： Christopher Haywood
发明人： Christopher Haywood
IPC分类号： G06F13/40 , G06F13/00 , G06F13/36 , G06F13/28 , G06F3/00
CPC分类号： G06F13/40 , G06F3/00 , G06F13/00 , G06F13/28 , G06F13/36
摘要： A computer-implemented method for transferring data from a computer system programmed to perform the method includes receiving in a memory buffer in a first memory module hosted by the computer system, a request for data stored in RAM of the first memory module from a host controller of the computer system, retrieving with the memory buffer, the data from the RAM, in response to the request, formatting with the memory buffer, the data from the RAM into formatted data in response to a defined software transport protocol, and initiating with the memory buffer, transfer of the formatted data to a storage destination external to the first memory module via an auxiliary interface of the memory buffer, bypassing the host controller of the computer system.
摘要翻译：用于从被编程为执行该方法的计算机系统传送数据的计算机实现的方法包括：在由计算机系统托管的第一存储器模块中的存储器缓冲器中接收来自主机控制器的存储在第一存储器模块的RAM中的数据的请求的计算机系统，响应于该请求，利用存储器缓冲器检索来自RAM的数据，根据定义的软件传输协议从RAM中将数据格式化为格式化数据，并且以存储器缓冲器，经由存储器缓冲器的辅助接口将格式化的数据传送到第一存储器模块外部的存储目的地，绕过计算机系统的主机控制器。

6. 发明授权

US06314106B1 Receive processing for dedicated bandwidth data communication switch backplane 失效
公开(公告)号：US06314106B1
公开(公告)日：2001-11-06
申请号：US09063493
申请日：1998-04-20
申请人： Wai King , Geoffrey C. Stone , Christopher Haywood
发明人： Wai King , Geoffrey C. Stone , Christopher Haywood
IPC分类号： H04L1228
CPC分类号： H04L49/351 , H04L45/7453 , H04L49/101 , H04L49/254 , H04L49/3018
摘要： A dedicated bandwidth switch backplane has efficient receive processing capable of handling highly parallel traffic. Packets must pass a filtering check and a watermark check before the receive port is allowed to release them to a queue. Highly efficient algorithms are applied to conduct the checks on the packets in a way which expedites receive processing and avoids contention. A hybrid priority/port-based arbitration algorithm is used to sequence filtering checks on pending packets. A watermark comparison algorithm performs preliminary calculations on the current packet using “projected” output queue write addresses for each possible outcome of the queueing decision on the preceding packet and using the actual outcome to select from among preliminary calculations to efficiently address the outcome-dependence of the current packet's watermark check on the queueing decision made on the preceding packet. Receive ports are operatively divided into full-write receive ports and selective-write receive ports for delivering their packets to the output queue. On the clock cycles where the selective-write receive port is assigned writing privileges, data is read from the queue, unless the selective-write receive port has indicated it wishes to write to the queue, in which case the selective-write receive port writes to the queue. The full-write receive ports always write data, if available, to the queue on the clock cycles where they are assigned writing privileges.

7. 发明授权

US08694857B2 Systems and methods for error detection and correction in a memory module which includes a memory buffer 有权
标题翻译：包括存储器缓冲器的存储器模块中用于错误检测和校正的系统和方法
公开(公告)号：US08694857B2
公开(公告)日：2014-04-08
申请号：US13445143
申请日：2012-04-12
申请人： David Wang , Christopher Haywood
发明人： David Wang , Christopher Haywood
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G06F11/10 , G11C7/1006 , G11C11/408 , G11C29/52 , G11C29/848 , G11C2029/0411 , H03M13/1515 , H03M13/152
摘要： The present systems include a memory module containing a plurality of RAM chips, typically DRAM, and a memory buffer arranged to buffer data between the DRAM and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words. One way in which this may be accomplished is by computing parity bits for each data word and storing them in parallel with each data word. The error detection and correction circuit can be arranged to detect and correct single errors, or multi-errors if the host controller includes its own error detection and correction circuit. Alternatively, the locations of faulty storage cells can be determined and stored in an address match table, which is then used to control multiplexers that direct data around the faulty cells, to redundant DRAM chips in one embodiment or to embedded SRAM in another.
摘要翻译：本系统包括存储模块，该存储器模块包含多个RAM芯片，通常为DRAM，以及一个存储器缓冲器，用于缓冲DRAM和主机控制器之间的数据。存储器缓冲器包括错误检测和校正电路，其布置成确保存储的数据字的完整性。可以实现这一点的一种方式是通过计算每个数据字的奇偶校验位并将它们与每个数据字并行存储。如果主机控制器包括自己的错误检测和校正电路，则可以将错误检测和校正电路设置为检测和纠正单个错误或多个错误。或者，可以确定故障存储单元的位置并将其存储在地址匹配表中，该地址匹配表然后被用于控制将故障单元周围的数据引导到冗余DRAM芯片或在另一实施例中的嵌入式SRAM。

8. 发明申请

US20130073802A1 Methods and Apparatus for Transferring Data Between Memory Modules 有权
标题翻译：用于在内存模块之间传输数据的方法和装置
公开(公告)号：US20130073802A1
公开(公告)日：2013-03-21
申请号：US13619692
申请日：2012-09-14
申请人： Christopher Haywood
发明人： Christopher Haywood
IPC分类号： G06F12/00
CPC分类号： G06F13/40 , G06F3/00 , G06F13/00 , G06F13/28 , G06F13/36
摘要： A computer-implemented method for transferring data from a computer system programmed to perform the method includes receiving in a memory buffer in a first memory module hosted by the computer system, a request for data stored in RAM of the first memory module from a host controller of the computer system, retrieving with the memory buffer, the data from the RAM, in response to the request, formatting with the memory buffer, the data from the RAM into formatted data in response to a defined software transport protocol, and initiating with the memory buffer, transfer of the formatted data to a storage destination external to the first memory module via an auxiliary interface of the memory buffer, bypassing the host controller of the computer system.
摘要翻译：用于从被编程为执行该方法的计算机系统传送数据的计算机实现的方法包括：在由计算机系统托管的第一存储器模块中的存储器缓冲器中接收来自主机控制器的存储在第一存储器模块的RAM中的数据的请求的计算机系统，响应于该请求，利用存储器缓冲器检索来自RAM的数据，根据定义的软件传输协议从RAM中将数据格式化为格式化数据，并且以存储器缓冲器，经由存储器缓冲器的辅助接口将格式化的数据传送到第一存储器模块外部的存储目的地，绕过计算机系统的主机控制器。

9. 发明申请

US20090300439A1 Method and Apparatus for Testing Write-Only Registers 审中-公开
标题翻译：用于测试只写寄存器的方法和设备
公开(公告)号：US20090300439A1
公开(公告)日：2009-12-03
申请号：US12132488
申请日：2008-06-03
申请人： Christopher Haywood
发明人： Christopher Haywood
IPC分类号： G11C29/00 , G06F11/22
CPC分类号： G11C29/52 , G11C29/1201
摘要： There is disclosed a test circuit for testing an integrated circuit containing at least one write-only register and providing at least one output signal through at least one output pin. The test circuit may include a test mode decoder circuit to enable a test mode and a data selector circuit to select at least a portion of data stored in the at least one write-only register as test data. The test data may be output from the integrated circuit through the at least one output pin.
摘要翻译：公开了一种用于测试包含至少一个只写寄存器并且通过至少一个输出引脚提供至少一个输出信号的集成电路的测试电路。测试电路可以包括测试模式解码器电路，以使测试模式和数据选择器电路能够选择存储在至少一个只写寄存器中的数据的至少一部分作为测试数据。测试数据可以通过至少一个输出引脚从集成电路输出。

10. 发明申请

US20060013225A1 Dedicated bandwidth data communication switch backplane 有权
公开(公告)号：US20060013225A1
公开(公告)日：2006-01-19
申请号：US11231920
申请日：2005-09-21
申请人： Christopher Haywood , Geoffrey Stone
发明人： Christopher Haywood , Geoffrey Stone
IPC分类号： H04L12/56
CPC分类号： H04L49/351 , H04L12/4641 , H04L45/7453 , H04L49/354
摘要： A LAN switch has a backplane matrix in which each controller has a dedicated packet bus for propagating packet data. Each bus has a root interfacing with the transmitting (root) controller and a plurality of leaves interfacing with receiving (leaf) controllers. This configuration enables each controller to simultaneously transmit packet data on the root of a bus and receive packet data off a plurality of leaves of other buses without contention. An efficient filtering and stalling system employed at the receive side of the backplane prevents the highly parallel traffic from causing receive side congestion.

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