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1. 发明申请

US20070196987A1 Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain 失效
标题翻译：具有嵌入式SiGe源极/漏极的假晶Si / SiGe / Si体器件
公开(公告)号：US20070196987A1
公开(公告)日：2007-08-23
申请号：US11358483
申请日：2006-02-21
申请人： Dureseti Chidambarrao , Anda Mocuta , Dan Mocuta , Carl Radens
发明人： Dureseti Chidambarrao , Anda Mocuta , Dan Mocuta , Carl Radens
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.
摘要翻译：本发明涉及半导体结构和制造方法，更具体地说涉及在PFET的源极/漏极区域中具有至少一个嵌入的SiGe层以及在NFET的沟道区域中至少一个嵌入的SiGe层的CMOS器件。在一个实施方案中，本发明的结构增强了NFET器件中的电子迁移率，并进一步提高了PFET器件中的空穴迁移率。此外，通过使用制造方法并因此实现本发明的最终结构，还可以在同一衬底上构造每个具有嵌入的SiGe层的PFET和NFET。

2. 发明申请

US20070252203A1 STRUCTURE AND METHOD FOR MANUFACTURING MOSFET WITH SUPER-STEEP RETROGRADED ISLAND 失效
标题翻译：具有超级退化岛的MOSFET制造结构和方法
公开(公告)号：US20070252203A1
公开(公告)日：2007-11-01
申请号：US11774221
申请日：2007-07-06
申请人： Huilong Zhu , Effendi Leobandung , Anda Mocuta , Dan Mocuta
发明人： Huilong Zhu , Effendi Leobandung , Anda Mocuta , Dan Mocuta
IPC分类号： H01L29/78
CPC分类号： H01L29/7842 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/105 , H01L29/1608 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffisivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.
摘要翻译：本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。低扩散层可以是Si 1-xy X z Z z，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或其组合。

3. 发明申请

US20060068555A1 Structure and method for manufacturing MOSFET with super-steep retrograded island 失效
标题翻译：具有超陡退化岛的MOSFET的制造和制造方法
公开(公告)号：US20060068555A1
公开(公告)日：2006-03-30
申请号：US10954838
申请日：2004-09-30
申请人： Huilong Zhu , Effendi Leobandung , Anda Mocuta , Dan Mocuta
发明人： Huilong Zhu , Effendi Leobandung , Anda Mocuta , Dan Mocuta
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/105 , H01L29/1608 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.
摘要翻译：本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。低扩散性层可以是Si 1-xy X z Z z，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或其组合。

4. 发明申请

US20060024934A1 CHEMICAL TREATMENT TO RETARD DIFFUSION IN A SEMICONDUCTOR OVERLAYER 失效
标题翻译：化学处理延缓半导体覆盖层的扩散
公开(公告)号：US20060024934A1
公开(公告)日：2006-02-02
申请号：US10710737
申请日：2004-07-30
申请人： Kevin Chan , Huajie Chen , Michael Gribelyuk , Judson Holt , Woo-Hyeong Lee , Ryan Mitchell , Renee Mo , Dan Mocuta , Werner Rausch , Paul Ronsheim , Henry Utomo
发明人： Kevin Chan , Huajie Chen , Michael Gribelyuk , Judson Holt , Woo-Hyeong Lee , Ryan Mitchell , Renee Mo , Dan Mocuta , Werner Rausch , Paul Ronsheim , Henry Utomo
IPC分类号： H01L21/22 , H01L21/331
CPC分类号： H01L21/28044 , H01L21/324
摘要： The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.
摘要翻译：本发明提供了一种用于延迟掺杂剂从第一材料层（通常为半导体）扩散到覆盖层或反之亦然的方法。在本发明的方法中，通过在两层之间形成包含碳和氧的单层来延缓掺杂剂从第一半导体扩散到覆层中或反之亦然。使用化学预处理方法在本发明中形成单层，其中使用包括碘和醇如甲醇的溶液。

5. 发明申请

US20050148161A1 Method of preventing surface roughening during hydrogen prebake of SiGe substrates 失效
公开(公告)号：US20050148161A1
公开(公告)日：2005-07-07
申请号：US10751208
申请日：2004-01-02
申请人： Huajie Chen , Dan Mocuta , Richard Murphy , Stephan Bedell , Devendra Sadana
发明人： Huajie Chen , Dan Mocuta , Richard Murphy , Stephan Bedell , Devendra Sadana
IPC分类号： C30B25/02 , C30B29/06 , C30B29/52 , H01L21/20 , H01L21/205 , H01L21/28 , H01L21/306 , H01L21/3205 , H01L21/36 , H01L21/44
CPC分类号： H01L21/02046 , C30B25/02 , C30B29/06 , C30B29/52 , H01L21/02052 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02658 , H01L21/02661 , Y10S438/933
摘要： The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves a first amount of oxygen (typically 1×1013-1×1015/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process which heats the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface sufficiently to remove additional oxygen from the surface and leave a second amount of oxygen, less than the first amount, on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The heating process leaves an amount of at least 5×1012/cm2 of oxygen (typically, between approximately 1×1013/cm2 and approximately 5×1013/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. By leaving a small amount of oxygen on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface, the heating processes avoid changing the roughness of the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. Then the process of epitaxially growing the epitaxial silicon-containing layer on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface is performed.

6. 发明申请

US20050148162A1 Method of preventing surface roughening during hydrogen pre-bake of SiGe substrates using chlorine containing gases 审中-公开
标题翻译：在使用含氯气体的SiGe衬底的氢预烘烤期间防止表面粗糙化的方法
公开(公告)号：US20050148162A1
公开(公告)日：2005-07-07
申请号：US10751207
申请日：2004-01-02
申请人： Huajie Chen , Dan Mocuta , Richard Murphy , Stephen Bedell , Devendra Sadana
发明人： Huajie Chen , Dan Mocuta , Richard Murphy , Stephen Bedell , Devendra Sadana
IPC分类号： C30B25/02 , C30B29/52 , H01L21/20 , H01L21/205 , H01L21/306 , H01L21/36 , H01L21/44
CPC分类号： H01L21/02046 , C30B25/02 , C30B29/52 , H01L21/02052 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02658 , H01L21/02661
摘要： The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves only a sub-monolayer of oxygen (typically 1×1013-1×1015/cm2 of oxygen) at the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process in a chlorine containing environment which heats the silicon germanium, strained silicon, or thin silicon-on-insulator surface sufficiently to remove the remaining oxygen from the surface. By introducing a small amount of chlorine containing gases, the heating processes avoid changing the roughness of the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. Then the process of epitaxially growing the epitaxial silicon-containing layer on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface is performed.
摘要翻译：本发明在硅锗，图案化的应变硅或图案化的绝缘体上硅表面上形成外延含硅层，并避免产生外延含硅层生长的粗糙表面。为了避免产生粗糙表面，本发明首先对硅锗，图案化应变硅或图案化的绝缘体上硅表面进行氢氟酸蚀刻工艺。该蚀刻工艺从表面除去大部分氧化物，并且仅留下氧气的亚单层（通常为1×10 13/1×10 15 / cm 2以上）的氧），图案化的应变硅或图案化的绝缘体上硅表面。然后，本发明在含氯环境中进行氢预烘烤过程，其中充分加热硅锗，应变硅或薄的绝缘体上硅表面以从表面除去剩余的氧。通过引入少量的含氯气体，加热过程避免改变硅锗，图案化的应变硅或图案化的绝缘体上硅表面的粗糙度。然后进行外延生长硅锗，图案化应变硅或图案化硅绝缘体表面上的外延硅含量层的工艺。

7. 发明授权

US06749684B1 Method for improving CVD film quality utilizing polysilicon getterer 有权
标题翻译：利用多晶硅吸收器提高CVD膜质量的方法
公开(公告)号：US06749684B1
公开(公告)日：2004-06-15
申请号：US10250181
申请日：2003-06-10
申请人： Huajie Chen , Dan Mocuta , Richard J. Murphy , Paul Ronsheim , David Rockwell
发明人： Huajie Chen , Dan Mocuta , Richard J. Murphy , Paul Ronsheim , David Rockwell
IPC分类号： C30B2504
CPC分类号： C30B29/06 , C30B25/02 , C30B29/08 , C30B29/52
摘要： A method is disclosed for forming an epitaxial layer on a front side of a substrate formed of a monocrystalline material, using a chemical vapor deposition system. In this method, a plurality of gettering wafers formed of a gettering material are arranged in the CVD system, such that the front side of each substrate is facing one of the gettering wafers. Impurities present in the CVD system during formation of the epitaxial layer are gettered by the gettering wafers. Alternatively, a layer of a gettering material is deposited on a back side of each of the plurality of substrates, and the substrates are arranged such that the front side of each substrate is facing the backside of another of the substrates. In another embodiment, a layer of a gettering material is deposited on an interior surface of the CVD system. Impurities removed from the CVD system during epitaxial formation include oxygen, water vapor and other oxygen-containing contaminants.
摘要翻译：公开了一种使用化学气相沉积系统在由单晶材料形成的基板的正面上形成外延层的方法。在该方法中，在CVD系统中配置由吸气材料形成的多个吸气晶片，使得每个基板的前侧面对吸气晶片之一。在形成外延层期间存在于CVD系统中的杂质被吸杂晶片吸收。或者，在多个基板的每一个的背面上沉积吸气材料层，并且将基板布置成使得每个基板的前侧面对另一个基板的背面。在另一个实施例中，吸气材料层沉积在CVD系统的内表面上。在外延形成期间从CVD系统中除去的杂质包括氧，水蒸气和其它含氧污染物。

8. 发明申请

US20070128840A1 Method of forming thin sgoi wafers with high relaxation and low stacking fault defect density 失效
标题翻译：形成具有高松弛和低堆垛缺陷缺陷密度的薄sgoi晶片的方法
公开(公告)号：US20070128840A1
公开(公告)日：2007-06-07
申请号：US10597066
申请日：2004-01-16
申请人： Huajie Chen , Stephen Bedell , Devendra Sadana , Dan Mocuta
发明人： Huajie Chen , Stephen Bedell , Devendra Sadana , Dan Mocuta
IPC分类号： H01L21/20
CPC分类号： H01L21/76256 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02664 , H01L21/31658 , H01L21/84 , H01L29/1054 , H01L29/78687
摘要： A method of forming a silicon germanium on insulator (SGOI) structure. A SiGe layer is deposited on an SOI wafer. Thermal mixing of the SiGe and Si layers is performed to form a thick SGOI with high relaxation and low stacking fault defect density. The SiGe layer is then thinned to a desired final thickness. The Ge concentration, the amount of relaxation, and stacking fault defect density are unchanged by the thinning process. A thin SGOI film is thus obtained with high relaxation and low stacking fault defect density. A layer of Si is then deposited on the thin SGOI wafer. The method of thinning includes low temperature (550° C.-700° C.) HIPOX or steam oxidation, in-situ HCl etching in an epitaxy chamber, or CMP. A rough SiGe surface resulting from HIPOX or steam oxidation thinning is smoothed with a touch-up CMP, in-situ hydrogen bake and SiGe buffer layer during strained Si deposition, or heating the wafer in a hydrogen environment with a mixture of gases HCl, DCS and GeH4.
摘要翻译：一种形成绝缘体上硅锗（SGOI）结构的方法。 SiGe层沉积在SOI晶片上。进行SiGe和Si层的热混合以形成具有高松弛和低堆垛层错缺陷密度的厚SGOI。然后将SiGe层变薄至所需的最终厚度。稀释过程，Ge浓度，松弛量和堆垛层错缺陷密度均不变。因此获得了具有高松弛和低堆垛层错缺陷密度的薄SGOI膜。然后在薄SGOI晶片上沉积一层Si。稀释方法包括低温（550℃-700℃）HIPOX或蒸汽氧化，在外延室中进行原位HCl蚀刻或CMP。由HIPOX或蒸汽氧化稀化产生的粗糙SiGe表面在应变Si沉积期间用接触式CMP，原位氢气烘烤和SiGe缓冲层进行平滑，或者在氢气环境中用HCl，DCS混合气体加热晶片和GeH 4。

9. 发明申请

US20070249112A1 DIFFERENTIAL SPACER FORMATION FOR A FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：场效应晶体管的差分空间形成
公开(公告)号：US20070249112A1
公开(公告)日：2007-10-25
申请号：US11308686
申请日：2006-04-21
申请人： Brian Geene , Dan Mocuta , Gaku Sudo
发明人： Brian Geene , Dan Mocuta , Gaku Sudo
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： A method for manufacturing an integrated circuit includes providing one or more n-type field effect transistor and one or more p-type field effect transistor on a semiconductor substrate. Each of the transistors separated by a trench isolation structure. Each of the transistors has a source and drain regions formed in the semiconductor layer and a gate electrode formed above the semiconductor layer. An oxide liner is deposited across the upper surface of the integrated circuit and onto each of the one or more n-type field effect transistors and one or more p-type field effect transistors. A nitride liner depositing is deposited the oxide liner. At least a portion of the nitride liner on each of the one or more p-type field effect transistor is removed to form nitride sidewall spacers. Additional source and drain regions are implanted into the one or more p-type field effect transistors. The integrated circuit is annealed. The nitride liner is removed from the one or more n-type field effect transistors. The exposed oxide liner is removed from the semiconductor substrate and the one or more n-type field effect transistors and the one or more p-type field effect transistors whereby each of the one or more p-type field effect transistor has greater silicide proximity than each of the one or more n-type field effect transistors, thereby allowing increased performance of each of the one or more p-type field effect transistors without adversely affecting performance of each of the one or more n-type field effect transistors.
摘要翻译：一种用于制造集成电路的方法包括在半导体衬底上提供一个或多个n型场效应晶体管和一个或多个p型场效应晶体管。每个晶体管由沟槽隔离结构分开。每个晶体管具有形成在半导体层中的源极和漏极区域以及形成在半导体层上方的栅电极。在集成电路的上表面和一个或多个n型场效应晶体管和一个或多个p型场效应晶体管中的每一个上沉积氧化物衬垫。氮化物衬垫沉积沉积氧化物衬垫。去除一个或多个p型场效应晶体管中的每一个上的氮化物衬垫的至少一部分，以形成氮化物侧壁间隔物。另外的源极和漏极区域被注入到一个或多个p型场效应晶体管中。集成电路退火。从一个或多个n型场效应晶体管去除氮化物衬垫。暴露的氧化物衬垫从半导体衬底和一个或多个n型场效应晶体管和一个或多个p型场效应晶体管中去除，由此，一个或多个p型场效应晶体管中的每一个与硅化物接近，每个一个或多个n型场效应晶体管，从而允许增加一个或多个p型场效应晶体管中的每一个的性能，而不会不利地影响一个或多个n型场效应晶体管中的每一个的性能。

10. 发明申请

US20050156154A1 Protecting Silicon Germanium Sidewall with Silicon for Strained Silicon/Silicon Germanium MOSFETs 失效
标题翻译：用硅保护硅锗侧壁，用于应变硅/硅锗MOSFET
公开(公告)号：US20050156154A1
公开(公告)日：2005-07-21
申请号：US10707840
申请日：2004-01-16
申请人： Huilong Zhu , Bruce Doris , Dan Mocuta
发明人： Huilong Zhu , Bruce Doris , Dan Mocuta
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/1054 , H01L29/66628 , H01L29/7834 , H01L29/7842 , H01L29/78618 , H01L29/78654
摘要： Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area.
摘要翻译：升高的Si / SiGe源极和漏极区域包括在SiGe侧壁上的外延生长的硅。 epi硅可防止Ge在硅化过程中的不利影响，包括Ge扩散和硅化物线断裂。 Si也增加了有效面积。

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