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1. 发明申请

US20070249112A1 DIFFERENTIAL SPACER FORMATION FOR A FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：场效应晶体管的差分空间形成
公开(公告)号：US20070249112A1
公开(公告)日：2007-10-25
申请号：US11308686
申请日：2006-04-21
申请人： Brian Geene , Dan Mocuta , Gaku Sudo
发明人： Brian Geene , Dan Mocuta , Gaku Sudo
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： A method for manufacturing an integrated circuit includes providing one or more n-type field effect transistor and one or more p-type field effect transistor on a semiconductor substrate. Each of the transistors separated by a trench isolation structure. Each of the transistors has a source and drain regions formed in the semiconductor layer and a gate electrode formed above the semiconductor layer. An oxide liner is deposited across the upper surface of the integrated circuit and onto each of the one or more n-type field effect transistors and one or more p-type field effect transistors. A nitride liner depositing is deposited the oxide liner. At least a portion of the nitride liner on each of the one or more p-type field effect transistor is removed to form nitride sidewall spacers. Additional source and drain regions are implanted into the one or more p-type field effect transistors. The integrated circuit is annealed. The nitride liner is removed from the one or more n-type field effect transistors. The exposed oxide liner is removed from the semiconductor substrate and the one or more n-type field effect transistors and the one or more p-type field effect transistors whereby each of the one or more p-type field effect transistor has greater silicide proximity than each of the one or more n-type field effect transistors, thereby allowing increased performance of each of the one or more p-type field effect transistors without adversely affecting performance of each of the one or more n-type field effect transistors.
摘要翻译：一种用于制造集成电路的方法包括在半导体衬底上提供一个或多个n型场效应晶体管和一个或多个p型场效应晶体管。每个晶体管由沟槽隔离结构分开。每个晶体管具有形成在半导体层中的源极和漏极区域以及形成在半导体层上方的栅电极。在集成电路的上表面和一个或多个n型场效应晶体管和一个或多个p型场效应晶体管中的每一个上沉积氧化物衬垫。氮化物衬垫沉积沉积氧化物衬垫。去除一个或多个p型场效应晶体管中的每一个上的氮化物衬垫的至少一部分，以形成氮化物侧壁间隔物。另外的源极和漏极区域被注入到一个或多个p型场效应晶体管中。集成电路退火。从一个或多个n型场效应晶体管去除氮化物衬垫。暴露的氧化物衬垫从半导体衬底和一个或多个n型场效应晶体管和一个或多个p型场效应晶体管中去除，由此，一个或多个p型场效应晶体管中的每一个与硅化物接近，每个一个或多个n型场效应晶体管，从而允许增加一个或多个p型场效应晶体管中的每一个的性能，而不会不利地影响一个或多个n型场效应晶体管中的每一个的性能。

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