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1. 发明申请

US20060228904A1 Protection of silicon from phosphoric acid using thick chemical oxide 有权
标题翻译：使用厚的化学氧化物保护硅的磷酸
公开(公告)号：US20060228904A1
公开(公告)日：2006-10-12
申请号：US11100530
申请日：2005-04-07
申请人： Deborah Riley , Brian Trentman , Brian Kirkpatrick
发明人： Deborah Riley , Brian Trentman , Brian Kirkpatrick
IPC分类号： H01L21/31
CPC分类号： H01L21/32139 , H01L21/02164 , H01L21/02238 , H01L21/28035 , H01L21/3086 , H01L21/31111 , H01L21/31662 , H01L21/32 , H01L21/76224
摘要： A method for protecting exposed silicon from attack by phosphoric acid during wet etching and stripping processes is provided. According to various embodiments of the method, a thick chemical oxide layer can be formed on the exposed silicon to protect the exposed portion from etching by phosphoric acid. The method can include exposing the silicon to at least one of a hot ozonated sulfuric acid and a hot peroxide sulfuric acid to form the thick chemical oxide.
摘要翻译：提供了一种在湿蚀刻和剥离过程中保护暴露的硅免受磷酸侵蚀的方法。根据该方法的各种实施例，可以在暴露的硅上形成厚的化学氧化物层，以保护暴露部分免受磷酸腐蚀。该方法可以包括将硅暴露于热臭氧化硫酸和热过氧化硫酸中的至少一种以形成厚的化学氧化物。

2. 发明申请

US20050090115A1 Post plasma clean process for a hardmask 有权
公开(公告)号：US20050090115A1
公开(公告)日：2005-04-28
申请号：US10692609
申请日：2003-10-24
申请人： Brian Kirkpatrick , Clint Montgomery , Brian Trentman , Randall Pak
发明人： Brian Kirkpatrick , Clint Montgomery , Brian Trentman , Randall Pak
IPC分类号： B08B7/00 , H01L21/02 , H01L21/304 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/76 , H01L21/762 , H01L21/302
CPC分类号： H01L21/02054 , H01L21/02063 , H01L21/31111 , H01L21/76224
摘要： The present invention provides a process of manufacturing a semiconductor device that comprises a process of manufacturing a semiconductor device that includes plasma etching 250 through a patterned hardmask layer 210 located over a semiconductor substrate 225 wherein the plasma etching forms a modified layer 210a on the hardmask layer 210, and removing at least a substantial portion of the modified layer 210a by exposing the modified layer 210a to a post plasma clean process.

3. 发明授权

US06930018B2 Shallow trench isolation structure and method 有权
标题翻译：浅沟隔离结构及方法
公开(公告)号：US06930018B2
公开(公告)日：2005-08-16
申请号：US10196089
申请日：2002-07-16
申请人： Freidoon Mehrad , Zhihao Chen , Shashank S. Ekbote , Brian Trentman
发明人： Freidoon Mehrad , Zhihao Chen , Shashank S. Ekbote , Brian Trentman
IPC分类号： H01L21/762 , H01L21/8222
CPC分类号： H01L21/76224
摘要： Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the formation thereof by growing a thin oxide layer on shallow isolation trench surfaces while preventing oxide formation on adjacent nitride surfaces, followed by the deposition of, and oxide growth upon, a polysilicon layer.
摘要翻译：公开了一种浅沟槽隔离（STI）结构及其制造方法。该方法消除了在制造STI结构时设计尺寸调整（DSA）的要求。进一步公开了一种STI沟槽衬垫及其形成方法，其通过在浅隔离沟槽表面上生长薄氧化物层，同时防止在相邻的氮化物表面上形成氧化物，随后在多晶硅层上沉积和氧化物生长。

4. 发明申请

US20050101101A1 FORMING A TRENCH TO DEFINE ONE OR MORE ISOLATION REGIONS IN A SEMICONDUCTOR STRUCTURE 有权
标题翻译：形成一个半导体结构中定义一个或多个隔离区域的TRENCH
公开(公告)号：US20050101101A1
公开(公告)日：2005-05-12
申请号：US10703387
申请日：2003-11-06
申请人： Juanita DeLoach , Freidoon Mehrad , Brian Trentman , Troy Yocum
发明人： Juanita DeLoach , Freidoon Mehrad , Brian Trentman , Troy Yocum
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232
摘要： In one embodiment, a method for forming a semiconductor structure in manufacturing a semiconductor device includes providing a pad layer on a surface of a substrate, providing a nitride layer on the pad layer, and providing a sacrificial oxide layer on the nitride layer. In a first etching step, at least the sacrificial oxide and nitride layers are etched to define opposing substantially vertical surfaces of at least the sacrificial oxide and nitride layers. In a second etching step, the nitride layer is etched such that the opposing substantially vertical surfaces of the nitride layer are recessed from the opposing substantially vertical surfaces of the sacrificial oxide layer, the sacrificial oxide layer substantially preventing the nitride layer from decreasing in thickness as a result of the etching of the nitride layer. In a third etching step, the substrate is etched to form a trench extending into the substrate for purposes of defining one or more isolation regions adjacent the trench.
摘要翻译：在一个实施例中，在制造半导体器件中形成半导体结构的方法包括在衬底的表面上提供焊盘层，在焊盘层上提供氮化物层，并在氮化物层上提供牺牲氧化物层。在第一蚀刻步骤中，至少牺牲氧化物层和氮化物层被蚀刻以限定至少牺牲氧化物层和氮化物层的相对的基本垂直的表面。在第二蚀刻步骤中，蚀刻氮化物层，使得氮化物层的相对的基本上垂直的表面从牺牲氧化物层的相对的基本上垂直的表面凹陷，牺牲氧化物层基本上防止氮化物层的厚度减小蚀刻氮化物层的结果。在第三蚀刻步骤中，蚀刻衬底以形成延伸到衬底中的沟槽，用于限定与沟槽相邻的一个或多个隔离区域。

5. 发明申请

US20050247994A1 Shallow trench isolation structure and method 审中-公开
公开(公告)号：US20050247994A1
公开(公告)日：2005-11-10
申请号：US11178935
申请日：2005-07-11
申请人： Freidoon Mehrad , Zhihao Chen , Shashank Ekbote , Brian Trentman
发明人： Freidoon Mehrad , Zhihao Chen , Shashank Ekbote , Brian Trentman
IPC分类号： H01L21/762 , H01L29/00
CPC分类号： H01L21/76224
摘要： Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the formation thereof by growing a thin oxide layer on shallow isolation trench surfaces while preventing oxide formation on adjacent nitride surfaces, followed by the deposition of, and oxide growth upon, a polysilicon layer.

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