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1. 发明申请

US20070117326A1 MATERIAL ARCHITECTURE FOR THE FABRICATION OF LOW TEMPERATURE TRANSISTOR 审中-公开
标题翻译：用于制造低温晶体管的材料结构
公开(公告)号：US20070117326A1
公开(公告)日：2007-05-24
申请号：US11625789
申请日：2007-01-22
申请人： Chung Tan , Jinping Liu , Hyeokjae Lee , Keng Tee , Elgin Quek
发明人： Chung Tan , Jinping Liu , Hyeokjae Lee , Keng Tee , Elgin Quek
IPC分类号： H01L27/148 , H01L21/336 , H01L21/425
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/1083 , H01L29/6659
摘要： A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
摘要翻译：在植入的PAI和/或掺杂区域的范围区域的末端的至少一部分中形成含碳层的结构和方法。含C层/区域从植入的PAI区域或掺杂区域吸收缺陷。示例性实施例示出了在FET下面的含C层。其它示例性实施方案显示了植入到植入的掺杂区域例如口袋区域，S / D区域和SDE区域的EOR区域中的植入的含C区域。可以使用低温退火，因为含碳层减少了缺陷。

2. 发明申请

US20060006427A1 Material architecture for the fabrication of low temperature transistor 有权
标题翻译：用于制造低温晶体管的材料结构
公开(公告)号：US20060006427A1
公开(公告)日：2006-01-12
申请号：US10886442
申请日：2004-07-07
申请人： Chung Tan , Jinping Liu , Hyeokjae Lee , Kheng Tee , Elgin Quek
发明人： Chung Tan , Jinping Liu , Hyeokjae Lee , Kheng Tee , Elgin Quek
IPC分类号： H01L27/148 , H01L21/425
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/1083
摘要： A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
摘要翻译：在植入的PAI和/或掺杂区域的范围区域的末端的至少一部分中形成含碳层的结构和方法。含C层/区域从植入的PAI区域或掺杂区域吸收缺陷。示例性实施例示出了在FET下面的含C层。其它示例性实施方案显示了植入到植入的掺杂区域例如口袋区域，S / D区域和SDE区域的EOR区域中的植入的含C区域。可以使用低温退火，因为含碳层减少了缺陷。

3. 发明授权

US07169675B2 Material architecture for the fabrication of low temperature transistor 有权
标题翻译：用于制造低温晶体管的材料结构
公开(公告)号：US07169675B2
公开(公告)日：2007-01-30
申请号：US10886442
申请日：2004-07-07
申请人： Chung Foong Tan , Jinping Liu , Hyeokjae Lee , Kheng Chok Tee , Elgin Quek
发明人： Chung Foong Tan , Jinping Liu , Hyeokjae Lee , Kheng Chok Tee , Elgin Quek
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/1083
摘要： A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
摘要翻译：在植入的PAI和/或掺杂区域的范围区域的末端的至少一部分中形成含碳层的结构和方法。含C层/区域从植入的PAI区域或掺杂区域吸收缺陷。示例性实施例示出了在FET下面的含C层。其它示例性实施方案显示了植入到植入的掺杂区域例如口袋区域，S / D区域和SDE区域的EOR区域中的植入的含C区域。可以使用低温退火，因为含碳层减少了缺陷。

4. 发明申请

US20050136623A1 Shallow amorphizing implant for gettering of deep secondary end of range defects 失效
标题翻译：浅非晶化植入物用于吸收深度范围缺陷的二次端
公开(公告)号：US20050136623A1
公开(公告)日：2005-06-23
申请号：US10743247
申请日：2003-12-22
申请人： Chung Tan , Hyeokjae Lee , Eng Chor , Elgin Quek
发明人： Chung Tan , Hyeokjae Lee , Eng Chor , Elgin Quek
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L21/322
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6656
摘要： A pocket implant process to reduce defects. We provide a gate structure, on a semiconductor substrate doped with a first conductivity type dopant. We perform a pocket amorphizing implantation procedure to form a pocket implant region adjacent to the gate structure, and an amorphous pocket region. Next, we perform a shallow amorphizing implant to form an amorphous shallow implant region. The amorphous shallow implant region being formed at a second depth above the amorphous pocket region. The substrate above the amorphous shallow implant region preferably remains crystalline. We perform a S/D implant procedure to form Deep S/D regions. We perform an anneal procedure preferably comprised of a first soak step and a second spike step to recrystalilze the amorphous shallow implant region and the amorphous pocket region, The defects created by the pocket implant are reduced by the shallow amorphous implant.
摘要翻译：口袋植入法减少缺陷。我们在掺杂有第一导电类型掺杂剂的半导体衬底上提供栅极结构。我们执行口袋非晶化植入程序以形成与栅极结构相邻的凹穴注入区域和无定形凹穴区域。接下来，我们执行浅非晶化植入物以形成无定形浅植入区域。非晶浅植入区域形成在无定形袋区域上方的第二深度处。非晶浅植入区域之上的衬底优选保持结晶。我们执行S / D植入程序以形成深S / D区域。我们执行优选由第一浸泡步骤和第二尖峰步骤组成的退火程序，以重结晶非晶浅注入区域和非晶质凹槽区域。由浅的非晶态植入物减少由凹穴注入产生的缺陷。

5. 发明授权

US07071069B2 Shallow amorphizing implant for gettering of deep secondary end of range defects 失效
标题翻译：浅非晶化植入物用于吸收深度范围缺陷的二次端
公开(公告)号：US07071069B2
公开(公告)日：2006-07-04
申请号：US10743247
申请日：2003-12-22
申请人： Chung Foong Tan , Hyeokjae Lee , Eng Fong Chor , Elgin Quek
发明人： Chung Foong Tan , Hyeokjae Lee , Eng Fong Chor , Elgin Quek
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6656
摘要： A pocket implant process to reduce defects. We provide a gate structure, on a semiconductor substrate doped with a first conductivity type dopant. We perform a pocket amorphizing implantation procedure to form a pocket implant region adjacent to the gate structure, and an amorphous pocket region. Next, we perform a shallow amorphizing implant to form an amorphous shallow implant region. The amorphous shallow implant region being formed at a second depth above the amorphous pocket region. The substrate above the amorphous shallow implant region preferably remains crystalline. We perform a S/D implant procedure to form Deep S/D regions. We perform an anneal procedure preferably comprised of a first soak step and a second spike step to recrystalilze the amorphous shallow implant region and the amorphous pocket region, The defects created by the pocket implant are reduced by the shallow amorphous implant.
摘要翻译：口袋植入法减少缺陷。我们在掺杂有第一导电类型掺杂剂的半导体衬底上提供栅极结构。我们执行口袋非晶化植入程序以形成与栅极结构相邻的凹穴注入区域和无定形凹穴区域。接下来，我们执行浅非晶化植入物以形成无定形浅植入区域。非晶浅植入区域形成在无定形袋区域上方的第二深度处。非晶浅植入区域之上的衬底优选保持结晶。我们执行S / D植入程序以形成深S / D区域。我们执行优选由第一浸泡步骤和第二尖峰步骤组成的退火程序，以重结晶非晶浅注入区域和非晶质凹槽区域。由浅的非晶态植入物减少由凹穴注入产生的缺陷。

6. 发明授权

US09362274B2 Self-aligned contact for replacement metal gate and silicide last processes 有权
公开(公告)号：US09362274B2
公开(公告)日：2016-06-07
申请号：US13867684
申请日：2013-04-22
申请人： Eng Huat Toh , Elgin Quek
发明人： Eng Huat Toh , Elgin Quek
IPC分类号： H01L29/76 , H01L27/088 , H01L21/8234 , H01L21/768 , H01L21/285 , H01L29/78
CPC分类号： H01L27/088 , H01L21/28518 , H01L21/76801 , H01L21/76816 , H01L21/76834 , H01L21/76897 , H01L21/823475 , H01L29/78
摘要： A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches.

7. 发明授权

US09064803B2 Split-gate flash memory exhibiting reduced interference 有权
标题翻译：分离式闪存表现出减小的干扰
公开(公告)号：US09064803B2
公开(公告)日：2015-06-23
申请号：US13189964
申请日：2011-07-25
申请人： Eng Huat Toh , Shyue Seng (Jason) Tan , Elgin Quek
发明人： Eng Huat Toh , Shyue Seng (Jason) Tan , Elgin Quek
IPC分类号： H01L21/28 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11517 , H01L21/28273 , H01L29/42328 , H01L29/513
摘要： A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.
摘要翻译：分离栅极存储单元由在栅极和存储器栅极堆叠之间的包含高k材料的介电隔离器制造。实施例包括具有包含低k和高k层的电介质间隔物的存储单元。其他实施例包括在字门和存储器栅叠层之间具有气隙的存储单元。

8. 发明授权

US08946806B2 Memory cell with decoupled channels 有权
标题翻译：具有解耦通道的存储单元
公开(公告)号：US08946806B2
公开(公告)日：2015-02-03
申请号：US13189554
申请日：2011-07-24
申请人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek , Yanzhe Tang
发明人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek , Yanzhe Tang
IPC分类号： H01L29/788 , H01L21/336 , G11C16/04 , H01L21/28 , H01L29/423 , H01L29/66 , H01L27/115
CPC分类号： H01L27/11568 , G11C16/04 , G11C16/0475 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11526 , H01L27/11573 , H01L29/42324 , H01L29/42328 , H01L29/42344 , H01L29/66825 , H01L29/7883
摘要： A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel.
摘要翻译：公开了一种具有由具有存储单元的存储单元区制备的衬底的器件。存储单元包括存取晶体管和存储晶体管。存取晶体管包括第一和第二源极/漏极（S / D）区域，并且存储晶体管包括第一和第二存储S / D区域。访问和存储晶体管串联耦合，第二S / D区域是公共S / D区域。擦除栅极设置在公共S / D区域上。在第一存储S / D区域上设置有编程门。存储器单元的这种布置使程序通道和擦除通道分离。

9. 发明申请

US20140070159A1 NOVEL RRAM STRUCTURE AT STI WITH SI-BASED SELECTOR 有权
标题翻译：基于SI的选择器的STI新型RRAM结构
公开(公告)号：US20140070159A1
公开(公告)日：2014-03-13
申请号：US13611817
申请日：2012-09-12
申请人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L21/02 , H01L45/00
CPC分类号： H01L27/2436 , H01L27/2445 , H01L45/08 , H01L45/124 , H01L45/146 , H01L45/1683
摘要： An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.
摘要翻译：公开了一种STI区域的RRAM，其具有垂直BJT选择器。实施例包括在衬底中限定STI区域，在衬底中注入掺杂剂以在STI区域底部周围和下方形成第一极性的阱，在STI区域的相对侧上的阱上具有第二极性的带，以及在基板的表面上的第二极性的每个带的第一极性的有源区域，在有源区上形成硬掩模，去除STI区域顶部以形成空腔，在腔侧和底表面上形成RRAM衬垫，在空腔中形成顶部电极，去除硬掩模的一部分以在空腔的相对侧上形成间隔物，以及将第二极性的掺杂剂注入远离空腔的每个有效区域的一部分。

10. 发明授权

US08119541B2 Modulation of stress in stress film through ion implantation and its application in stress memorization technique 有权
标题翻译：通过离子注入调制应力薄膜中的应力及其在应力记忆技术中的应用
公开(公告)号：US08119541B2
公开(公告)日：2012-02-21
申请号：US12510276
申请日：2009-07-28
申请人： Lee Wee Teo , Elgin Quek
发明人： Lee Wee Teo , Elgin Quek
IPC分类号： H01L21/469 , H01L21/31
CPC分类号： H01L21/823807 , H01L21/823864
摘要： Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.
摘要翻译：本发明的一些示例性实施例提供了一种通过增加通道区域中的应力来改善MOS器件的性能的方法。用于NMOS晶体管的示例性实施例是在NMOS晶体管上形成拉伸应力层。对应力层进行重离子注入，然后进行退火。这增加了由栅极保持/存储的应力层的应力量，从而提高了器件性能。

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