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1. 发明授权

US08638636B2 Word line decoder circuit apparatus and method 有权
标题翻译：字线解码电路装置及方法
公开(公告)号：US08638636B2
公开(公告)日：2014-01-28
申请号：US12816960
申请日：2010-06-16
申请人： Shin-Jang Shen , Bo-Chang Wu , Chuan Ying Yu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Shin-Jang Shen , Bo-Chang Wu , Chuan Ying Yu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C8/00
CPC分类号： G11C16/16
摘要： One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.
摘要翻译：该技术的一个实施例是一种装置，存储器集成电路。存储器集成电路具有字线地址解码电路。该电路允许选择单个字线以具有擦除电压。解码器电路包括反相器和逻辑。逆变器具有输入和控制字线的输出以执行擦除操作。输入的电压范围在第一参考电压和第二电压基准之间延伸。电压基准的示例是电压源和地。在一些实施例中，该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。解码器的逻辑电路由字线地址控制，以在擦除操作期间确定反相器的输入值。

2. 发明申请

US20110069571A1 Word Line Decoder Circuit Apparatus and Method 有权
标题翻译：字线解码器电路设备及方法
公开(公告)号：US20110069571A1
公开(公告)日：2011-03-24
申请号：US12816960
申请日：2010-06-16
申请人： Shin-Jang Shen , Bo-Chang Wu , Chuan Ying Yu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Shin-Jang Shen , Bo-Chang Wu , Chuan Ying Yu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C7/00 , G11C8/10
CPC分类号： G11C16/16
摘要： One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.
摘要翻译：该技术的一个实施例是一种装置，存储器集成电路。存储器集成电路具有字线地址解码电路。该电路允许选择单个字线以具有擦除电压。解码器电路包括反相器和逻辑。逆变器具有输入和控制字线的输出以执行擦除操作。输入的电压范围在第一参考电压和第二电压基准之间延伸。电压基准的示例是电压源和地。在一些实施例中，该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。解码器的逻辑电路由字线地址控制，以在擦除操作期间确定反相器的输入值。

3. 发明授权

US08982640B2 Method and apparatus for reducing erase disturb of memory by using recovery bias 有权
标题翻译：通过使用恢复偏压来减少存储器的擦除干扰的方法和装置
公开(公告)号：US08982640B2
公开(公告)日：2015-03-17
申请号：US13426985
申请日：2012-03-22
申请人： Chun Hsiung Hung , Bo-Chang Wu , Kuen-Long Chang , Ken-Hui Chen
发明人： Chun Hsiung Hung , Bo-Chang Wu , Kuen-Long Chang , Ken-Hui Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/3431 , G11C16/14 , G11C16/3418 , G11C16/344
摘要： A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.
摘要翻译：非易失性存储器阵列被分成多个存储器组。非易失性存储器阵列接收擦除命令以擦除第一组存储器组，而不是第二组存储器组。控制电路响应于擦除命令来擦除第一组存储器组，通过应用恢复偏压布置来调整第二组存储器组的至少一个存储器组中的存储器单元的阈值电压。通过将恢复偏压装置应用于第二组存储器组的至少一个存储器组中的存储器单元，至少部分地在恢复偏压装置期间校正擦除干扰。

4. 发明申请

US20130250675A1 Method and Apparatus for Reducing Erase Disturb of Memory By Using Recovery Bias 有权
标题翻译：用于通过使用恢复偏压来减少存储器擦除干扰的方法和装置
公开(公告)号：US20130250675A1
公开(公告)日：2013-09-26
申请号：US13426985
申请日：2012-03-22
申请人： Chun Hsiung Hung , Bo-Chang Wu , Kuen-Long Chang , Ken-Lui Chen
发明人： Chun Hsiung Hung , Bo-Chang Wu , Kuen-Long Chang , Ken-Lui Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/3431 , G11C16/14 , G11C16/3418 , G11C16/344
摘要： A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.
摘要翻译：非易失性存储器阵列被分成多个存储器组。非易失性存储器阵列接收擦除命令以擦除第一组存储器组，而不是第二组存储器组。控制电路响应于擦除命令来擦除第一组存储器组，通过应用恢复偏压布置来调整第二组存储器组的至少一个存储器组中的存储器单元的阈值电压。通过将恢复偏压装置应用于第二组存储器组的至少一个存储器组中的存储器单元，至少部分地在恢复偏压装置期间校正擦除干扰。

5. 发明申请

US20090122451A1 ESD PROTECTION CIRCUIT DEVICE 审中-公开
标题翻译： ESD保护电路设备
公开(公告)号：US20090122451A1
公开(公告)日：2009-05-14
申请号：US11936803
申请日：2007-11-08
申请人： Meng-Yong Lin , Bo-Chang Wu , Wei-Yang Ou , Chi-Mo Huang
发明人： Meng-Yong Lin , Bo-Chang Wu , Wei-Yang Ou , Chi-Mo Huang
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： The present invention discloses an ESD (ELECTRO-STATIC DISCHARGE) protection circuit device, the ESD (ELECTRO-STATIC DISCHARGE) protection circuit device includes a first switching device having a first terminal coupled to a first signal; a first control device coupled to the first signal for generating a first control signal according to the first signal; a second switching device having a first terminal coupled to a second signal, a second terminal coupled to a second terminal of the first switching device; and a second control device coupled to the second signal and a control terminal of the first switching device for generating a second control signal according to the second signal; wherein the first control signal coupled to the control terminal of the second switching device, and the second control signal coupled to the control terminal of the first switching device.
摘要翻译：本发明公开了一种ESD（ELECTRO-STATIC DISCHARGE）电路保护电路装置，其中ESD（ELECTRO-STATIC DISCHARGE）保护电路装置包括具有与第一信号耦合的第一端子的第一开关装置; 耦合到所述第一信号的第一控制装置，用于根据所述第一信号产生第一控制信号; 第二开关装置，具有耦合到第二信号的第一端子，耦合到第一开关装置的第二端子的第二端子; 以及耦合到所述第二信号的第二控制装置和所述第一开关装置的控制端，用于根据所述第二信号产生第二控制信号; 其中所述第一控制信号耦合到所述第二开关装置的控制端，并且所述第二控制信号耦合到所述第一开关装置的控制端。

6. 发明申请

US20090164859A1 DRIVING CIRCUIT OF DISPLAY APPARATUS AND DRIVING METHOD THEREOF 审中-公开
标题翻译：显示设备的驱动电路及其驱动方法
公开(公告)号：US20090164859A1
公开(公告)日：2009-06-25
申请号：US12042323
申请日：2008-03-04
申请人： Ming-Huang Liu , Wen-Chi Wu , Meng-Yong Lin , Bo-Chang Wu , Chi-Mo Huang
发明人： Ming-Huang Liu , Wen-Chi Wu , Meng-Yong Lin , Bo-Chang Wu , Chi-Mo Huang
IPC分类号： G01R31/28
CPC分类号： G09G3/3677 , G09G2310/0267 , G09G2310/0289
摘要： A driving circuit of a display apparatus includes a decoder coupled to a plurality of scan lines of a display panel for decoding a plurality of input signals to output a plurality of scan line driving signals to thereby enable at least one scan line of the plurality of scan lines, and a plurality of control units (respectively coupled to the plurality of scan lines) for receiving an output enable signal to disable the plurality of scan lines during an interval between two scan lines being enabled.
摘要翻译：显示装置的驱动电路包括耦合到显示面板的多条扫描线的解码器，用于对多个输入信号进行解码以输出多条扫描线驱动信号，从而使得多条扫描中的至少一条扫描线线路和多个控制单元（分别耦合到多条扫描线），用于接收输出使能信号以在启用两条扫描线之间的间隔期间禁用多条扫描线。

7. 发明授权

US07459953B1 Voltage adjusting circuit 有权
标题翻译：电压调节电路
公开(公告)号：US07459953B1
公开(公告)日：2008-12-02
申请号：US11838863
申请日：2007-08-14
申请人： Meng-Yong Lin , Bo-Chang Wu , Ming-Huang Liu , Chi-Mo Huang
发明人： Meng-Yong Lin , Bo-Chang Wu , Ming-Huang Liu , Chi-Mo Huang
IPC分类号： H03K17/687 , H03K5/08
CPC分类号： H03K19/018507
摘要： The present invention discloses a voltage adjusting circuit including a first switch element, a second switch element, a third switch element, a fourth switch element, a fifth switch element, and a sixth switch element. At first, the voltage adjusting circuit performs a discharging operation on an output voltage toward a reference voltage source, and then when the output voltage level is approaching a voltage level of an input voltage source, the voltage adjusting circuit will perform the discharging operation on the output voltage toward the input voltage source instead, and thus the voltage adjusting circuit can avoid affecting the input voltage source when performing the discharging operation. In addition, the voltage adjusting circuit does not need a digital counter to perform the above dual-phase type discharging operation or multi-phase type discharging operation, and therefore cost of the voltage adjusting circuit is lower, and the voltage adjusting circuit has good accuracy.
摘要翻译：本发明公开了一种电压调节电路，包括第一开关元件，第二开关元件，第三开关元件，第四开关元件，第五开关元件和第六开关元件。首先，电压调整电路对基准电压源的输出电压进行放电动作，然后，当输出电压电平接近输入电压源的电压电平时，电压调整电路对其进行放电动作输出电压代替输入电压，因此电压调整电路可以避免在进行放电操作时影响输入电压源。此外，电压调整电路不需要数字计数器来执行上述双相放电操作或多相放电操作，因此电压调节电路的成本较低，并且电压调节电路具有良好的精度。

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