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1. 发明授权

US07007036B2 Method and apparatus for embedding configuration data 失效
公开(公告)号：US07007036B2
公开(公告)日：2006-02-28
申请号：US10109285
申请日：2002-03-28
申请人： Christopher J. McCarty , Stephen B. Johnson , Brad D. Besmer
发明人： Christopher J. McCarty , Stephen B. Johnson , Brad D. Besmer
IPC分类号： G06F7/00
CPC分类号： G06F9/44505 , Y10S707/99931 , Y10S707/99943
摘要： The present invention provides an apparatus and a method for embedding information from a first configuration data set having data structures into an embedded processing system, wherein embedding the information maintains user-defined variables. Embedding information includes comparing a first identifier from the first configuration data set with a second identifier from a second configuration data set having data structures to determine if the first identifier differs from the second identifier. In response to a determination of the first identifier differing from the second identifier, a decision is made to merge the first configuration data set with the second configuration data set to form a merged configuration data set. Afterwards, the merged configuration data set is written to the embedded processing system, wherein the merged configuration data set includes maintained user-defined variables.

2. 发明授权

US07590819B2 Compact memory management unit 有权
标题翻译：紧凑型内存管理单元
公开(公告)号：US07590819B2
公开(公告)日：2009-09-15
申请号：US11124536
申请日：2005-05-09
申请人： Stephen B. Johnson , Brad D. Besmer , Timothy E. Hoglund , Jana L. Richards
发明人： Stephen B. Johnson , Brad D. Besmer , Timothy E. Hoglund , Jana L. Richards
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F12/0292
摘要： A memory management unit (MMU) for a device controller that provides enhanced functionality while maintaining a small physical size or footprint, such that the die size required to manufacture the memory management unit circuitry within the device controller integrated circuit device remains small notwithstanding such enhanced functionality. This compact/tiny MMU provides virtual memory addressing and memory error detection functionality while maintaining a small physical die size. The small physical die size with enhanced functionality is obtained by improvements in translating virtual to physical addressing without use of extensive translation tables, which themselves would otherwise consume memory and associated die real estate. In addition, the MMU allows a firmware image containing code and data segments to be run-time swapped between internal shared context RAM and external memory.
摘要翻译：一种用于设备控制器的存储器管理单元（MMU），其在保持小的物理尺寸或占地面积的同时提供增强的功能，使得制造设备控制器集成电路设备内的存储器管理单元电路所需的管芯尺寸仍然很小，尽管具有这种增强的功能。这种紧凑型/微型MMU提供虚拟内存寻址和内存错误检测功能，同时保持较小的物理裸片大小。具有增强功能的小型物理尺寸通过改进虚拟到物理寻址的改进而获得，而不使用广泛的翻译表，其本身将消耗存储器和相关的裸片空间。此外，MMU允许包含代码和数据段的固件映像在内部共享上下文RAM和外部存储器之间进行运行时交换。

3. 发明授权

US07054972B2 Apparatus and method for dynamically enabling and disabling interrupt coalescing in data processing system 有权
标题翻译：在数据处理系统中动态启用和禁用中断合并的装置和方法
公开(公告)号：US07054972B2
公开(公告)日：2006-05-30
申请号：US10319206
申请日：2002-12-13
申请人： Owen N. Parry , Brad D. Besmer , Stephen B. Johnson
发明人： Owen N. Parry , Brad D. Besmer , Stephen B. Johnson
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： An apparatus and method for dynamically enabling and disabling interrupt coalescing in a data processing system. The present invention involves consistently monitoring IO load on an IOP of an IO adapter. The firmware on the IO adapter may have a global variable that stores counters for PCI function registers. Each counter tracks the number of outstanding IOs of a corresponding PCI function register. The counter is incremented whenever a new IO is received and is decremented upon posting the completed message back to the OS. A timer interrupt is generated periodically so that an ISR may be periodically performed. In the ISR, the maximum value stored of each counter seen since last timer interrupt is analyzed. When the maximum value stored is greater than a predetermined threshold value, the interrupt coalescing is enabled.
摘要翻译：一种用于在数据处理系统中动态地启用和禁用中断合并的装置和方法。本发明涉及持续监视IO适配器的IOP上的IO负载。 IO适配器上的固件可能有一个全局变量，用于存储PCI功能寄存器的计数器。每个计数器跟踪相应PCI功能寄存器的未完成IO的数量。每当接收到新的IO时，计数器递增，并且在将完成的消息发回操作系统后递减。周期性地产生定时中断，以便周期性地执行ISR。在ISR中，分析从上一次定时器中断以来看到的每个计数器存储的最大值。当存储的最大值大于预定阈值时，中断合并被使能。

4. 发明授权

US07155569B2 Method for raid striped I/O request generation using a shared scatter gather list 有权
公开(公告)号：US07155569B2
公开(公告)日：2006-12-26
申请号：US10184667
申请日：2002-06-28
申请人： Stephen B. Johnson , Brad D. Besmer
发明人： Stephen B. Johnson , Brad D. Besmer
IPC分类号： G06F13/14
CPC分类号： G06F3/0601 , G06F2003/0697
摘要： A code efficient transfer method in response to a single host I/O request generates a single scatter gather list. The disk array controller transforms the single host I/O request into multiple physical I/O requests. Each of these multiple physical I/O requests uses the single scatter gather list to perform the data transfer operation. Each physical I/O request corresponds to the data transfer of one data stripe. The data stripe is an initial or header stripe of about 0.5K or a stripe of at least 64K.

5. 发明授权

US06629229B1 Message index descriptor 失效
标题翻译：消息索引描述符
公开(公告)号：US06629229B1
公开(公告)日：2003-09-30
申请号：US09864760
申请日：2001-05-24
申请人： Christopher J. McCarty , Stephen B. Johnson
发明人： Christopher J. McCarty , Stephen B. Johnson
IPC分类号： G06F1202
CPC分类号： G06F13/387
摘要： A circuit comprising a memory, a queue, and a translator. The memory may be configured to store a message at an address at least as great as a base address. The queue may be configured to store a descriptor, wherein the descriptor is configured to have (i) an index, (ii) a routing field, and (iii) fewer bits than the address. The translator may be configured to translate between the address and the index.
摘要翻译：包括存储器，队列和转换器的电路。存储器可以被配置为在至少与基地址一样大的地址处存储消息。队列可以被配置为存储描述符，其中描述符被配置为具有（i）索引，（ii）路由字段，和（iii）比地址少的比特。翻译器可以被配置为在地址和索引之间进行转换。

6. 发明授权

US07111301B1 Request and completion queue load balancing 有权
标题翻译：请求和完成队列负载均衡
公开(公告)号：US07111301B1
公开(公告)日：2006-09-19
申请号：US09972330
申请日：2001-10-05
申请人： Stephen B. Johnson , Christopher J. McCarty
发明人： Stephen B. Johnson , Christopher J. McCarty
IPC分类号： G06F9/46 , G06F3/06
CPC分类号： H04L49/901 , H04L47/125 , H04L49/90
摘要： An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a request count in response to a request head pointer and a request tail pointer. The second circuit may be configured to generate a completion count in response a completion head pointer and a completion tail pointer. The third circuit may be configured to prioritize an interrupt in response to the request and completion counts.
摘要翻译：一种包括第一电路，第二电路和第三电路的装置。第一电路可以被配置为响应于请求头指针和请求尾指针来生成请求计数。第二电路可以被配置为响应于完成头指针和完成尾指针来产生完成计数。第三电路可以被配置为响应于请求和完成计数来对中断进行优先级排序。

7. 发明授权

US06868492B1 Methods and apparatus for booting a host adapter device devoid of nonvolatile program memory 失效
标题翻译：用于引导没有非易失性程序存储器的主机适配器设备的方法和装置
公开(公告)号：US06868492B1
公开(公告)日：2005-03-15
申请号：US09910088
申请日：2001-07-20
申请人： Christopher J. McCarty , Stephen B. Johnson
发明人： Christopher J. McCarty , Stephen B. Johnson
IPC分类号： G06F9/445
CPC分类号： G06F9/4411
摘要： Methods and associated structure for booting host adapter devices in a system where the host adapter devices are devoid of independent, nonvolatile memory devices for storage of programmed instructions operable within the intelligent host adapter device. The operational programmed instructions for the intelligent host adapter device are stored in the nonvolatile memory of the system motherboard along with the standard BIOS code of the system. The intelligent host adapter device operational programmed instructions are then downloaded by the BIOS code into the host adapter's volatile local program memory to initialize operation of the intelligent host adapter device. Further, device driver code operable in the operating system on the motherboard will upload the previously downloaded programmed instructions from the intelligent host adapter so that the programmed instructions may be reloaded to the host adapter in response to reset conditions, power management events, and other conditions.
摘要翻译：用于在主机适配器设备没有用于存储可在智能主机适配器设备中操作的编程指令的独立的非易失性存储器设备的系统中引导主机适配器设备的方法和相关联的结构。智能主机适配器设备的操作编程指令与系统的标准BIOS代码一起存储在系统主板的非易失性存储器中。然后，智能主机适配器设备的操作编程指令通过BIOS代码下载到主机适配器的易失性本地程序存储器中，以初始化智能主机适配器设备的操作。此外，可在主板上的操作系统中操作的设备驱动程序代码将从智能主机适配器上载先前下载的编程指令，使得编程指令可以响应于复位条件，电源管理事件和其他条件被重新加载到主机适配器。

8. 发明授权

US06842792B2 Method and/or apparatus to sort request commands for SCSI multi-command packets 有权
标题翻译：用于对SCSI多命令分组的请求命令进行排序的方法和/或装置
公开(公告)号：US06842792B2
公开(公告)日：2005-01-11
申请号：US10183670
申请日：2002-06-27
申请人： Stephen B. Johnson , Bradley D. Besmer , Guy W. Kendall , Christopher J. McCarty , Andrew C. Brown
发明人： Stephen B. Johnson , Bradley D. Besmer , Guy W. Kendall , Christopher J. McCarty , Andrew C. Brown
IPC分类号： G06F3/00 , G06F13/12 , G06F13/14
CPC分类号： G06F13/126
摘要： An apparatus comprising a plurality of IO queues and a logic circuit. The plurality of IO queues each may be configured to receive a respective IO request and present the IO request in response to a trigger signal. The logic circuit may be configured to (a) (i) receive one or more of the IO requests and (ii) serially coalesce the IO requests in response to a respective device identification (ID) of the IO requests, and (iii) present one or more of the coalesced IO requests as one or more respective context queue requests in response to the trigger signal and (b) generate the trigger signal when a current queue count is equal to a maximum queue depth.
摘要翻译：一种包括多个IO队列和逻辑电路的装置。多个IO队列可以被配置为接收相应的IO请求并响应于触发信号呈现IO请求。逻辑电路可以被配置为：（i）（i）响应于IO请求的相应设备标识（ID），接收IO请求中的一个或多个并且（ii）串行地合并IO请求，以及（iii）呈现一个或多个合并的IO请求作为响应于触发信号的一个或多个相应的上下文队列请求，以及（b）当当前队列计数等于最大队列深度时产生触发信号。

9. 发明授权

US07913023B2 Specifying lanes for SAS wide port connections 有权
标题翻译：指定SAS宽端口连接的通道
公开(公告)号：US07913023B2
公开(公告)日：2011-03-22
申请号：US12384287
申请日：2009-04-02
申请人： Stephen B. Johnson , Christopher McCarty
发明人： Stephen B. Johnson , Christopher McCarty
IPC分类号： G06F13/00 , G06F13/40
CPC分类号： G06F13/4022
摘要： The optimal lanes of at least one SAS wide port for the data connection are discovered. The allowable lanes for the data connection within the SAS wide ports of each level of the SAS domain are specified. The specified allowable lanes for the data connection are checked. The data connection is created on the specified allowable lanes.
摘要翻译：发现数据连接的至少一个SAS宽端口的最佳通道。指定SAS域各级SAS宽端口中数据连接的允许通道。检查数据连接的指定允许通道。数据连接是在指定的允许通道上创建的。

10. 发明授权

US07849248B2 Method and system for combining multiple serial attached small computer system interface (SAS) expanders 有权
标题翻译：用于组合多个串行连接的小型计算机系统接口（SAS）扩展器的方法和系统
公开(公告)号：US07849248B2
公开(公告)日：2010-12-07
申请号：US12384289
申请日：2009-04-02
申请人： Stephen B. Johnson , Timothy E. Hoglund , Louis H. Odenwald, Jr.
发明人： Stephen B. Johnson , Timothy E. Hoglund , Louis H. Odenwald, Jr.
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： At least one first numbered phy of a first SAS expander is grouped with at least one second numbered phy of a second SAS expander physically separate from the first SAS expander into at least one common SAS wide port. An identical SAS address is assigned to the first SAS expander and the second SAS expander for operating the first SAS expander and the second SAS expander to behave and respond as a single, cohesive SAS expander. The first SAS expander is directly connected to the second SAS expander for inter-expander communications.
摘要翻译：第一SAS扩展器的至少一个第一编号的phy与第二SAS扩展器的至少一个第二编号的phy分组，其与第一SAS扩展器物理分离成至少一个公共SAS宽端口。分配相同的SAS地址到第一个SAS扩展器和第二个SAS扩展器，用于操作第一个SAS扩展器和第二个SAS扩展器，使其作为一个单一的，内聚的SAS扩展器来运行和响应。第一个SAS扩展器直接连接到第二个SAS扩展器，用于扩展器间通信。

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