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1. 发明授权

US08495534B2 Post-placement cell shifting 失效
标题翻译：放置后细胞转移
公开(公告)号：US08495534B2
公开(公告)日：2013-07-23
申请号：US12796550
申请日：2010-06-08
申请人： Charles J. Alpert , Zhuo D. Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh E. Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo D. Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh E. Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块。扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。扩张器也可能使这些细胞膨胀并合法化。

2. 发明授权

US08347257B2 Detailed routability by cell placement 有权
标题翻译：细胞放置的详细路线
公开(公告)号：US08347257B2
公开(公告)日：2013-01-01
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

3. 发明申请

US20110302544A1 POST-PLACEMENT CELL SHIFTING 失效
标题翻译：后置放电细胞移位
公开(公告)号：US20110302544A1
公开(公告)日：2011-12-08
申请号：US12796550
申请日：2010-06-08
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块。扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。扩张器也可能使这些细胞膨胀并合法化。

4. 发明申请

US20110302545A1 DETAILED ROUTABILITY BY CELL PLACEMENT 有权
标题翻译：细节放置的详细的不可靠性
公开(公告)号：US20110302545A1
公开(公告)日：2011-12-08
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

5. 发明授权

US08347249B2 Incremental timing optimization and placement 有权
标题翻译：增量时序优化和放置
公开(公告)号：US08347249B2
公开(公告)日：2013-01-01
申请号：US12416754
申请日：2009-04-01
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
IPC分类号： G06F9/455
CPC分类号： G06F17/505
摘要： Disclosed is a computer implemented method, data processing system, and computer program product to optimize, incrementally, a circuit design. An Electronic Design Automation (EDA) system receives a plurality of nets wherein each net is comprised of at least one pin. Each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net. The second pin can be a member of a second net, and the path is associated with a slack. The EDA system determines whether the path is a critical path based on the slack. The EDA system reduces at least one wire length of the path, responsive to a determination that the path is a critical path. The EDA system moves a non-critical component in order to reduce at least one wire length of the nets that include pins of a non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path. The EDA system legalizes the components on a net having a pin selected from the first pin and the second pin. The EDA system determines whether a component is a non-critical component. The EDA system, responsive to a determination that component is a non-critical component, legalizes the non-critical component. The EDA system incrementally optimizes a time delay of the plurality of paths, responsive to legalizing.
摘要翻译：公开了一种计算机实现的方法，数据处理系统和计算机程序产品，以优化，递增地进行电路设计。电子设计自动化（EDA）系统接收多个网络，其中每个网络由至少一个引脚组成。每个销连接到网以形成至少第一销和第二销的路径，其中第一销是第一网的成员。第二个引脚可以是第二个网络的一个成员，并且该路径与一个松弛相关联。 EDA系统确定路径是否是基于松弛的关键路径。响应于确定路径是关键路径，EDA系统减少路径的至少一个线长度。 EDA系统移动非关键部件，以便响应于减少路径的至少一个线长度来减少包括非关键部件的引脚的网络的至少一个线长度，其中非关键部件缺少关键路径上的引脚。 EDA系统使具有从第一引脚和第二引脚选择的引脚的网络上的部件合法化。 EDA系统确定组件是否是非关键组件。 EDA系统响应于组件是非关键组件的确定，使非关键组件合法化。响应于合法化，EDA系统递增地优化多个路径的时间延迟。

6. 发明申请

US20100257498A1 INCREMENTAL TIMING OPTIMIZATION AND PLACEMENT 有权
标题翻译：增量时序优化和放置
公开(公告)号：US20100257498A1
公开(公告)日：2010-10-07
申请号：US12416754
申请日：2009-04-01
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed is a computer implemented method, data processing system, and computer program product to optimize, incrementally, a circuit design. An Electronic Design Automation (EDA) system receives a plurality of nets wherein each net is comprised of at least one pin. Each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net. The second pin can be a member of a second net, and the path is associated with a slack. The EDA system determines whether the path is a critical path based on the slack. The EDA system reduces at least one wire length of the path, responsive to a determination that the path is a critical path. The EDA system moves a non-critical component in order to reduce at least one wire length of the nets that include pins of a non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path. The EDA system legalizes the components on a net having a pin selected from the first pin and the second pin. The EDA system determines whether a component is a non-critical component. The EDA system, responsive to a determination that component is a non-critical component, legalizes the non-critical component. The EDA system incrementally optimizes a time delay of the plurality of paths, responsive to legalizing.
摘要翻译：公开了一种计算机实现的方法，数据处理系统和计算机程序产品，以优化，递增地进行电路设计。电子设计自动化（EDA）系统接收多个网络，其中每个网络由至少一个引脚组成。每个销连接到网以形成至少第一销和第二销的路径，其中第一销是第一网的成员。第二个引脚可以是第二个网络的一个成员，并且该路径与一个松弛相关联。 EDA系统确定路径是否是基于松弛的关键路径。响应于确定路径是关键路径，EDA系统减少路径的至少一个线长度。 EDA系统移动非关键部件，以便响应于减少路径的至少一个线长度来减少包括非关键部件的引脚的网络的至少一个线长度，其中非关键部件缺少关键路径上的引脚。 EDA系统使具有从第一引脚和第二引脚选择的引脚的网络上的部件合法化。 EDA系统确定组件是否是非关键组件。 EDA系统响应于组件是非关键组件的确定，使非关键组件合法化。响应于合法化，EDA系统递增地优化多个路径的时间延迟。

7. 发明申请

US20120297355A1 WHITESPACE CREATION AND PRESERVATION IN CIRCUIT DESIGN 审中-公开
标题翻译：电路设计中的创新和保存
公开(公告)号：US20120297355A1
公开(公告)日：2012-11-22
申请号：US13112098
申请日：2011-05-20
申请人： Charles Jay Alpert , Gi-Joon Nam , Shyam Ramji , Jarrod Alexander Roy , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles Jay Alpert , Gi-Joon Nam , Shyam Ramji , Jarrod Alexander Roy , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method, system, and computer program product for whitespace creation and preservation in the design of an integrated circuit (IC) are provided in the illustrative embodiments. A first estimate is formed by estimating an amount of whitespace that is needed to reduce a congestion value of a congested area of the design to a threshold value. A set of virtual filler cells is added to the congested area, wherein adding the set of virtual filler cells does not add actual whitespace cells to the congested area but reduces the congested area by at least the first estimate. A virtual filler cell in the set of virtual filler cells is replaced with a corresponding real filler cell. A determination is made whether the design has improved. A final placement solution is created when the design has not improved.
摘要翻译：在说明性实施例中提供了用于集成电路（IC）设计中的空白创建和保存的方法，系统和计算机程序产品。通过估计将设计的拥塞区域的拥塞值减少到阈值所需的空白量来形成第一估计。将一组虚拟填充单元添加到拥塞区域，其中添加虚拟填充单元组不会向拥塞区域添加实际空白单元，而是至少通过第一估计减少拥塞区域。虚拟填充单元组中的虚拟填充单元被替换为相应的真实填充单元。确定设计是否改进。当设计没有改进时，创建最终的布局解决方案。

8. 发明申请

US20140007036A1 SEPARATE REFINEMENT OF LOCAL WIRELENGTH AND LOCAL MODULE DENSITY IN INTERMEDIATE PLACEMENT OF AN INTEGRATED CIRCUIT DESIGN 有权
标题翻译：集成电路设计的中间位置的局部线性和局部模块密度的单独修正
公开(公告)号：US20140007036A1
公开(公告)日：2014-01-02
申请号：US13539440
申请日：2012-06-30
申请人： Charles J. Alpert , Myung-Chul Kim , Gi-Joon Nam , Shyam Ramji , Natarajan Viswanathan
发明人： Charles J. Alpert , Myung-Chul Kim , Gi-Joon Nam , Shyam Ramji , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： After a global placement phase of physical design of an integrated circuit, a data processing system iteratively refines local placement of a plurality of modules comprising the integrated circuit within a die area based on density of the plurality of modules and separately refines local wirelength for the plurality of modules in individual subareas among a plurality of subareas of the die area. The data processing system thereafter performs detailed placement of modules in the plurality of subareas.
摘要翻译：在集成电路的物理设计的全局放置阶段之后，数据处理系统基于多个模块的密度迭代地将包括该集成电路的多个模块的本地放置精细化，并单独地对多个模块中的局部线长进行精细化在模具区域的多个子区域中的各个子区域中的模块。此后，数据处理系统在多个子区域中执行模块的详细布置。

9. 发明授权

US08595675B1 Local objective optimization in global placement of an integrated circuit design 失效
标题翻译：集成电路设计的全局放置中的局部目标优化
公开(公告)号：US08595675B1
公开(公告)日：2013-11-26
申请号：US13539428
申请日：2012-06-30
申请人： Charles J. Alpert , Myung-Chul Kim , Gi-Joon Nam , Shyam Ramji , Natarajan Viswanathan
发明人： Charles J. Alpert , Myung-Chul Kim , Gi-Joon Nam , Shyam Ramji , Natarajan Viswanathan
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5072
摘要： A global placement phase of physical design of an integrated circuit includes iteratively spreading a plurality of modules comprising the integrated circuit within a die area based on density of the plurality of modules and optimizing module placement by preserving global module density while improving a local objective, such as local wirelength and/or local density, in individual subareas among a plurality of subareas of the die area. After global placement, detailed placement of modules in the plurality of subareas is performed.
摘要翻译：集成电路的物理设计的全局放置阶段包括基于多个模块的密度迭代地扩展包含该集成电路的多个模块，并且通过保持全局模块密度来优化模块放置，同时改善本地目标，例如作为模具区域的多个子区域中的各个子区域中的局部线长度和/或局部密度。在全局放置之后，执行在多个子区域中的模块的详细放置。

10. 发明授权

US08769457B2 Separate refinement of local wirelength and local module density in intermediate placement of an integrated circuit design 有权
标题翻译：在集成电路设计的中间放置中，局部电线长度和局部模块密度分别细化
公开(公告)号：US08769457B2
公开(公告)日：2014-07-01
申请号：US13539440
申请日：2012-06-30
申请人： Charles J. Alpert , Myung-Chul Kim , Gi-Joon Nam , Shyam Ramji , Natarajan Viswanathan
发明人： Charles J. Alpert , Myung-Chul Kim , Gi-Joon Nam , Shyam Ramji , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： After a global placement phase of physical design of an integrated circuit, a data processing system iteratively refines local placement of a plurality of modules comprising the integrated circuit within a die area based on density of the plurality of modules and separately refines local wirelength for the plurality of modules in individual subareas among a plurality of subareas of the die area. The data processing system thereafter performs detailed placement of modules in the plurality of subareas.
摘要翻译：在集成电路的物理设计的全局放置阶段之后，数据处理系统基于多个模块的密度迭代地将包括该集成电路的多个模块的本地放置精细化，并单独地对多个模块中的局部线长进行精细化在模具区域的多个子区域中的各个子区域中的模块。此后，数据处理系统在多个子区域中执行模块的详细布置。

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