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    • 1. 发明授权
    • Multi-phase clock generator
    • 多相时钟发生器
    • US08405436B2
    • 2013-03-26
    • US13186076
    • 2011-07-19
    • Chan-Fei LinShih-Chun Lin
    • Chan-Fei LinShih-Chun Lin
    • H03L7/06
    • H03L7/07H03K5/135H03L7/0812
    • A multi-phase clock generator including a first delay locked loop, a reference signal generator and a second delay locked loop is provided. The first delay locked loop generates 2N phase clock signals according to an input clock signal, so as to equally divide a clock period of the input clock signal into 2N predetermined phases, where N is a positive integer. The reference signal generator selects two phase clock signals according to a digital signal, and adjusts an output ratio of the two phase clock signals in 2M clock periods to serve as a reference clock signal. The second delay locked loop delays a first phase clock signal according to a phase difference between the reference clock signal and an output clock signal. In this way, each predetermined phase is further equally divided into 2M sub-phases, so that the multi-phase clock generator has 2(N+M) phase selections.
    • 提供了包括第一延迟锁定环路,参考信号发生器和第二延迟锁定环路的多相时钟发生器。 第一延迟锁定环根据输入时钟信号产生2N个相位时钟信号,以便将输入时钟信号的时钟周期等分成2N个预定相位,其中N是正整数。 参考信号发生器根据数字信号选择两相时钟信号,并在2M个时钟周期内调整两相时钟信号的输出比,作为参考时钟信号。 第二延迟锁定环根据参考时钟信号和输出时钟信号之间的相位差延迟第一相位时钟信号。 以这种方式,每个预定相位被进一步等分成2M个子相,使得多相时钟发生器具有2(N + M)个相位选择。
    • 2. 发明申请
    • MULTI-PHASE CLOCK GENERATOR
    • 多相时钟发生器
    • US20130022162A1
    • 2013-01-24
    • US13186076
    • 2011-07-19
    • Chan-Fei LinShih-Chun Lin
    • Chan-Fei LinShih-Chun Lin
    • H04L7/00
    • H03L7/07H03K5/135H03L7/0812
    • A multi-phase clock generator including a first delay locked loop, a reference signal generator and a second delay locked loop is provided. The first delay locked loop generates 2N phase clock signals according to an input clock signal, so as to equally divide a clock period of the input clock signal into 2N predetermined phases, where N is a positive integer. The reference signal generator selects two phase clock signals according to a digital signal, and adjusts an output ratio of the two phase clock signals in 2M clock periods to serve as a reference clock signal. The second delay locked loop delays a first phase clock signal according to a phase difference between the reference clock signal and an output clock signal. In this way, each predetermined phase is further equally divided into 2M sub-phases, so that the multi-phase clock generator has 2(N+M) phase selections.
    • 提供了包括第一延迟锁定环路,参考信号发生器和第二延迟锁定环路的多相时钟发生器。 第一延迟锁定环根据输入时钟信号产生2N个相位时钟信号,以便将输入时钟信号的时钟周期等分成2N个预定相位,其中N是正整数。 参考信号发生器根据数字信号选择两相时钟信号,并在2M个时钟周期内调整两相时钟信号的输出比,作为参考时钟信号。 第二延迟锁定环根据参考时钟信号和输出时钟信号之间的相位差延迟第一相位时钟信号。 以这种方式,每个预定相位被进一步等分成2M个子相,使得多相时钟发生器具有2(N + M)个相位选择。
    • 3. 发明申请
    • PHASE SELECTOR
    • 相位选择器
    • US20110255867A1
    • 2011-10-20
    • US12759886
    • 2010-04-14
    • Wen-Teng FanChan-Fei LinShih-Chun Lin
    • Wen-Teng FanChan-Fei LinShih-Chun Lin
    • H04J14/00
    • H03K5/135H03K2005/00052H03L7/0812
    • A phase selector including a plurality of buffers, a multiplexer, a first inverter, and a selecting circuit is provided. Each of the buffers provides a clock signal, and the clock signals have different phases. The multiplexer selectively outputs one of the clock signals as a switch signal according to a first control signal, wherein the first control signal is first portion of bits of a selecting signal. The input terminal of the first inverter receives a second control signal, wherein the second control signal is second portion of bits of the selecting signal, and the output terminal of the first inverter outputs an inverted signal. The selecting circuit transmits the second control signal of the selecting signal or the inverted signal to the output terminal of the phase selector according to the logic state of the switch signal.
    • 提供了包括多个缓冲器的相位选择器,多路复用器,第一反相器和选择电路。 每个缓冲器提供时钟信号,并且时钟信号具有不同的相位。 复用器根据第一控制信号选择性地输出其中一个时钟信号作为开关信号,其中第一控制信号是选择信号的位的第一部分。 第一反相器的输入端接收第二控制信号,其中第二控制信号是选择信号的位的第二部分,第一反相器的输出端输出反相信号。 选择电路根据开关信号的逻辑状态将选择信号或反相信号的第二控制信号发送到相位选择器的输出端。
    • 4. 发明授权
    • Phase selector
    • 相位选择器
    • US08222941B2
    • 2012-07-17
    • US12759886
    • 2010-04-14
    • Wen-Teng FanChan-Fei LinShih-Chun Lin
    • Wen-Teng FanChan-Fei LinShih-Chun Lin
    • H03L7/00
    • H03K5/135H03K2005/00052H03L7/0812
    • A phase selector including a plurality of buffers, a multiplexer, a first inverter, and a selecting circuit is provided. Each of the buffers provides a clock signal, and the clock signals have different phases. The multiplexer selectively outputs one of the clock signals as a switch signal according to a first control signal, wherein the first control signal is first portion of bits of a selecting signal. The input terminal of the first inverter receives a second control signal, wherein the second control signal is second portion of bits of the selecting signal, and the output terminal of the first inverter outputs an inverted signal. The selecting circuit transmits the second control signal of the selecting signal or the inverted signal to the output terminal of the phase selector according to the logic state of the switch signal.
    • 提供了包括多个缓冲器的相位选择器,多路复用器,第一反相器和选择电路。 每个缓冲器提供时钟信号,并且时钟信号具有不同的相位。 复用器根据第一控制信号选择性地输出其中一个时钟信号作为开关信号,其中第一控制信号是选择信号的位的第一部分。 第一反相器的输入端接收第二控制信号,其中第二控制信号是选择信号的位的第二部分,第一反相器的输出端输出反相信号。 选择电路根据开关信号的逻辑状态将选择信号或反相信号的第二控制信号发送到相位选择器的输出端。
    • 6. 发明申请
    • SPREAD-SPECTRUM GENERATOR
    • 扩频发生器
    • US20110038397A1
    • 2011-02-17
    • US12540817
    • 2009-08-13
    • Wen-Teng FanShih-Chun Lin
    • Wen-Teng FanShih-Chun Lin
    • H04B1/69
    • H04B15/06H04B2215/064H04B2215/067
    • A spread-spectrum generator is provided. The spread-spectrum generator includes a delay module and a control module. The delay module is controlled by a first control signal to delay an input signal by a delay time, and thereby generate a delay signal. The control module is coupled to the delay module for detecting a first edge of the delay signal, and thereby generating the first control signal. Accordingly, the spread-spectrum generator can spread the frequency of the input signal by delaying the input signal by various delay time, and the spread-spectrum generator can also reduce electromagnetic interference (EMI).
    • 提供扩频发生器。 扩频发生器包括延迟模块和控制模块。 延迟模块由第一控制信号控制,以将输入信号延迟延迟时间,从而产生延迟信号。 控制模块耦合到延迟模块,用于检测延迟信号的第一边缘,从而产生第一控制信号。 因此,扩频发生器可以通过延迟输入信号各种延迟时间来扩展输入信号的频率,扩频发生器也可以减小电磁干扰(EMI)。
    • 7. 发明授权
    • Low-fire microwave dielectric compositions
    • 低火微波介电组合物
    • US06309993B1
    • 2001-10-30
    • US09301009
    • 1999-04-28
    • Jau-Ho JeanShih-Chun Lin
    • Jau-Ho JeanShih-Chun Lin
    • C03C3091
    • C03C8/20C03C3/091C03C14/004C03C2214/04C03C2214/30
    • The present invention relates to a dielectric composition which can be densified at a temperature no higher than 1000° C. and can provide ceramic products with a dielectric constant of 20 to 45 and a quality constant of 1000 to 1300 at 7 GHz. The dielectric composition comprises 20-90 vol % borosilicate glass and 10-80 vol % TiO2 ceramic. Multilayered microwave dielectric ceramic elements can be prepared by mixing the composition of the present invention with an organic solvent, a polymer binder and a plasticizer, forming a green sheet from the mixture by tape casting, screen-printing and laminating the green sheet, and then cofiring the multilayer ceramic laminate with a high electrical conductivity metal, such as Ag and Cu.
    • 本发明涉及一种电介质组合物,其可以在不高于1000℃的温度下致密化,并且可以在7GHz下提供介电常数为20至45,质量常数为1000至1300的陶瓷产品。 电介质组合物包含20-90体积%的硼硅酸盐玻璃和10-80体积%的TiO 2陶瓷。 多层微波介电陶瓷元件可以通过将本发明的组合物与有机溶剂,聚合物粘合剂和增塑剂混合来制备,通过带式浇铸,丝网印刷和层压生坯从混合物形成生片,然后 用诸如Ag和Cu的高导电性金属共烧多层陶瓷层压体。
    • 9. 发明申请
    • Timing Controller and Clock Signal Detection Circuit Thereof
    • 定时控制器及其时钟信号检测电路
    • US20110216057A1
    • 2011-09-08
    • US12719649
    • 2010-03-08
    • Wen-Teng FANShih-Chun Lin
    • Wen-Teng FANShih-Chun Lin
    • G06F3/038H03L7/06
    • G06F3/038H03L7/06
    • The clock signal detection circuit includes a lock detection circuit, a duty cycle detection circuit, a first logic circuit, and a counter. The lock detection circuit detects whether an input clock signal and a feedback clock signal of a delay locked loop are in phase. The duty cycle detection circuit detects whether the duty cycle of the input clock signal is within a percentage range. The first logic circuit, electrically connected to the lock detection circuit and the duty cycle detection circuit, outputs a detecting result signal which is at first logic level when the input clock signal are in phase with the feedback clock signal, and the duty cycle of the input clock signal is within a percentage range. The counter outputs a lock detection signal which is at the first logic level when the detecting result signal has maintained at the first logic level for a first constant period of time.
    • 时钟信号检测电路包括锁定检测电路,占空比检测电路,第一逻辑电路和计数器。 锁定检测电路检测延迟锁定环路的输入时钟信号和反馈时钟信号是否同相。 占空比检测电路检测输入时钟信号的占空比是否在百分比范围内。 与锁定检测电路和占空比检测电路电连接的第一逻辑电路输出当输入时钟信号与反馈时钟信号同相时处于第一逻辑电平的检测结果信号, 输入时钟信号在百分比范围内。 当检测结果信号在第一恒定时间段内保持在第一逻辑电平时,计数器输出处于第一逻辑电平的锁定检测信号。
    • 10. 发明授权
    • Ceramic dielectric compositions
    • 陶瓷电介质组合物
    • US06174829B1
    • 2001-01-16
    • US09226117
    • 1999-01-07
    • Jau-Ho JeanShih-Chun Lin
    • Jau-Ho JeanShih-Chun Lin
    • C03C1400
    • C03C14/004C03C14/00C03C2214/04C03C2214/17H05K1/0306
    • A low-fire, low-dielectric ceramic composition is disclosed. The ceramic composition comprises a mixture of finely divided particles consisting of 30-90% by volume of Ca—Ba—Al—Zn—Si glass and 70-10% by volume of oxides, which can be densified up to 95% at temperatures of 800-1000° C. The sintered body produced thereby exhibits a dielectric constant in the range of 6-10 and a dielectric loss in the range of 0.01%-0.5% at 1 MHz. The ceramic composition can be processed with organic solvent, polymeric binder and plasticizer to produce a green sheet which is co-firable with high electrical conductivity metal such as gold, silver, silver-palladium and copper.
    • 公开了一种低火低介电陶瓷组合物。 陶瓷组合物包含由30-90体积%的Ca-Ba-Al-Zn-Si玻璃和70-10体积%的氧化物组成的细碎颗粒的混合物,其可以在 800-1000℃。由此产生的烧结体在1MHz的介电常数范围为6-10,介电损耗为0.01%-0.5%。 陶瓷组合物可以用有机溶剂,聚合物粘合剂和增塑剂加工,以生产与金,银,银 - 钯和铜等高导电性金属共同使用的生片。