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1. 发明授权

US5376844A Programmable logic device with multiplexer-based programmable interconnections 失效
标题翻译：可编程逻辑器件，具有基于复用器的可编程互连
公开(公告)号：US5376844A
公开(公告)日：1994-12-27
申请号：US39944
申请日：1993-03-29
申请人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
发明人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/17736
摘要： A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
摘要翻译：可编程逻辑阵列集成电路具有被分组成多个相互排斥的组的多个可编程逻辑元件。每个组包括与该组唯一相关联的信号导体，用于在该组中的可编程逻辑元件之间传送信号。提供其他信号导体用于在组之间传送信号。多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。

2. 发明授权

US5485103A Programmable logic array with local and global conductors 失效
标题翻译：具有局部和全局导体的可编程逻辑阵列
公开(公告)号：US5485103A
公开(公告)日：1996-01-16
申请号：US356516
申请日：1994-12-15
申请人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
发明人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/17736
摘要： A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
摘要翻译：可编程逻辑阵列集成电路具有被分组成多个相互排斥的组的多个可编程逻辑元件。每个组包括与该组唯一相关联的信号导体，用于在该组中的可编程逻辑元件之间传送信号。提供其他信号导体用于在组之间传送信号。多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。

3. 发明授权

US5436575A Programmable logic array integrated circuits 失效
公开(公告)号：US5436575A
公开(公告)日：1995-07-25
申请号：US111693
申请日：1993-08-25
申请人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
发明人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
IPC分类号： G11C8/12 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , G11C8/12 , H03K19/1737 , H03K19/17704
摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

4. 发明授权

US5260610A Programmable logic element interconnections for programmable logic array integrated circuits 失效
标题翻译：可编程逻辑阵列集成电路的可编程逻辑元件互连
公开(公告)号：US5260610A
公开(公告)日：1993-11-09
申请号：US754017
申请日：1991-09-03
申请人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
发明人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/17736
摘要： A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

5. 发明授权

US06294928B1 Programmable logic device with highly routable interconnect 失效
标题翻译：具有高度可路由互连的可编程逻辑器件
公开(公告)号：US06294928B1
公开(公告)日：2001-09-25
申请号：US08838398
申请日：1997-04-03
申请人： Craig S. Lytle , Kerry S. Veenstra , Francis B. Heile
发明人： Craig S. Lytle , Kerry S. Veenstra , Francis B. Heile
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , H03K19/177 , H03K19/17728
摘要： A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. A LAB (A-200) comprises an input multiplexer region (A-504), logic elements (A-300), input-output pins (A-516), and output multiplexer region (A-508). Furthermore, a logic device and a method of operating a logic device. The device includes logic elements (B-240) that perform desired logic functions and routing functions. The logic elements (B-240) are arranged in larger logic blocks known as logic array blocks (B-230) that have local interconnection systems. The logic array blocks (B-230) are configured to provide global interconnections. The configuration provides a Clos network, whereby a signal may be routed from any input to any output without blocking.
摘要翻译：具有高可路由可编程互连结构的可编程逻辑器件架构。逻辑阵列块（LAB），可编程互连结构和其他逻辑元件的布置形成了Clos网络。在满足特定约束之后，保证架构的路由。当中间阶段没有扇出的时候，这个架构是可行的。 AAB（A-200）包括输入多路复用器区域（A-504），逻辑元件（A-300），输入输出引脚（A-516）和输出多路复用器区域（A-508）。此外，逻辑设备和操作逻辑设备的方法。该设备包括执行所需逻辑功能和路由功能的逻辑元件（B-240）。逻辑元件（B-240）被布置在具有本地互连系统的被称为逻辑阵列块（B-230）的较大逻辑块中。逻辑阵列块（B-230）被配置为提供全局互连。该配置提供了一个Clos网络，从而信号可以从任何输入路由到任何输出而不阻塞。

6. 发明授权

US06492834B1 Programmable logic device with highly routable interconnect 失效
标题翻译：具有高度可路由互连的可编程逻辑器件
公开(公告)号：US06492834B1
公开(公告)日：2002-12-10
申请号：US09687215
申请日：2001-02-01
申请人： Craig S. Lytle , Kerry S. Veenstra
发明人： Craig S. Lytle , Kerry S. Veenstra
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. A LAB (200) comprises an input multiplexer region (504), logic elements (300), input-output pins (516), and output multiplexer region (508).
摘要翻译：具有高可路由可编程互连结构的可编程逻辑器件架构。逻辑阵列块（LAB），可编程互连结构和其他逻辑元件的布置形成了Clos网络。在满足特定约束之后，保证架构的路由。当中间阶段没有扇出的时候，这个架构是可行的。 LAB（200）包括输入多路复用器区域（504），逻辑元件（300），输入输出引脚（516）和输出多路复用器区域（508）。

7. 发明授权

US06181162B2 Programmable logic device with highly routable interconnect 失效
标题翻译：具有高度可路由互连的可编程逻辑器件
公开(公告)号：US06181162B2
公开(公告)日：2001-01-30
申请号：US09003261
申请日：1998-01-06
申请人： Craig S. Lytle , Kerry S. Veenstra
发明人： Craig S. Lytle , Kerry S. Veenstra
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , H03K19/17728
摘要： A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. A LAB (200) comprises an input multiplexer region (504), logic elements (300), input-output pins (516), and output multiplexer region (508).
摘要翻译：具有高可路由可编程互连结构的可编程逻辑器件架构。逻辑阵列块（LAB），可编程互连结构和其他逻辑元件的布置形成了Clos网络。在满足特定约束之后，保证架构的路由。当中间阶段没有扇出的时候，这个架构是可行的。 LAB（200）包括输入多路复用器区域（504），逻辑元件（300），输入输出引脚（516）和输出多路复用器区域（508）。

8. 发明授权

US4677318A Programmable logic storage element for programmable logic devices 失效
标题翻译：可编程逻辑器件的可编程逻辑存储元件
公开(公告)号：US4677318A
公开(公告)日：1987-06-30
申请号：US722684
申请日：1985-04-12
申请人： Kerry S. Veenstra
发明人： Kerry S. Veenstra
IPC分类号： H03K3/037 , H03K19/173 , H03K19/177
CPC分类号： H03K3/037 , H03K19/17716
摘要： A storage element for use in a logic array including a flip-flop device and a complex logic circuit interconnected in such a way that the output of the complex logic circuit is an input to the flip-flop. A Toggle Flip-Flop Control (TFFC) signal, an invert control (INV) signal, and a clock (CLK) signal are also inputs to the complex logic circuit. The output of the flip-flop connects to an output pad, an internal direct feedback line which is one of the means by which the flip-flop is connected to the comples logic circuit, and an external feedback bus which leads back to an associated AND-OR array. The inptu to the complex logic circuit is generated by the standard AND-OR array which is programmable to some degree.
摘要翻译：一种存储元件，用于包括触发器件和复合逻辑电路的逻辑阵列，所述复合逻辑电路以复合逻辑电路的输出为触发器的输入。触发触发器控制（TFFC）信号，反相控制（INV）信号和时钟（CLK）信号也是复合逻辑电路的输入。触发器的输出连接到输出焊盘，内部直接反馈线，其是触发器连接到压缩逻辑电路的手段之一，以及引导到相关联的AND的外部反馈总线 -OR数组。复杂逻辑电路的输入由标准AND-OR阵列产生，该阵列在某种程度上是可编程的。

9. 发明授权

US06525678B1 Configuring a programmable logic device 有权
标题翻译：配置可编程逻辑器件
公开(公告)号：US06525678B1
公开(公告)日：2003-02-25
申请号：US09972674
申请日：2001-10-05
申请人： Kerry S. Veenstra , Boon Jin Ang
发明人： Kerry S. Veenstra , Boon Jin Ang
IPC分类号： H03M500
CPC分类号： H03M7/3088 , G11B20/1426 , H03M5/145 , H03M7/30 , H03M7/40 , H03M7/46
摘要： A programmable logic device (PLD) can be configured using configuration data stored on a memory. The configuration data is compressed using a compression algorithm before being stored on the memory. When the PLD is to be configured, the compressed configuration data is read from the memory, decompressed, then loaded onto the PLD.
摘要翻译：可以使用存储在存储器上的配置数据来配置可编程逻辑器件（PLD）。在存储在存储器之前，使用压缩算法对配置数据进行压缩。当要配置PLD时，从存储器中读取压缩的配置数据，解压缩，然后加载到PLD上。

10. 发明授权

US06605960B2 Programmable logic configuration device with configuration memory accessible to a second device 有权
标题翻译：可编程逻辑配置设备，配置存储器可由第二个设备访问
公开(公告)号：US06605960B2
公开(公告)日：2003-08-12
申请号：US10038470
申请日：2002-01-03
申请人： Kerry S. Veenstra , Boon-Jin Ang
发明人： Kerry S. Veenstra , Boon-Jin Ang
IPC分类号： G06F738
CPC分类号： G06F17/5054
摘要： A programmable logic configuration device is disclosed having a configuration memory accessible by a controller of the configuration device and by a second device. Arbitration circuitry is provided for arbitrating access to the configuration memory between the configuration controller and the second device.
摘要翻译：公开了一种可编程逻辑配置装置，其具有由配置装置的控制器和第二装置可访问的配置存储器。提供仲裁电路用于仲裁访问配置控制器和第二设备之间的配置存储器。

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