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1. 发明授权

US07089135B2 Event based IC test system 失效
标题翻译：基于事件的IC测试系统
公开(公告)号：US07089135B2
公开(公告)日：2006-08-08
申请号：US10150777
申请日：2002-05-20
申请人： Rochit Rajsuman , Shigeru Sugamori , Robert F. Sauer , Hiroaki Yamoto , James Alan Turnquist , Bruce R. Parnas , Anthony Le
发明人： Rochit Rajsuman , Shigeru Sugamori , Robert F. Sauer , Hiroaki Yamoto , James Alan Turnquist , Bruce R. Parnas , Anthony Le
IPC分类号： G01R31/00
CPC分类号： G01R31/31813 , G01R31/318307 , G01R31/318342 , G01R31/31917 , G01R31/31919 , G01R31/31928
摘要： An event based test system for testing an IC device under test (DUT) designed under an automatic electronic design (EDA) environment. The event based test system includes an event memory for storing event data derived directly from simulation of design data for an intended IC in the EDA environment where the event data to denote each event is formed with time index indicating a time length from a predetermined point and an event type indicating a type of change at an event, an event generation unit for generating test vectors based on the event data where waveform of each vector is determined by the event type and a timing of the waveform is determined by accumulating the time index of previous events, and means for supplying test vectors to the DUT and evaluating response outputs of the DUT at predetermined timings.
摘要翻译：一种基于事件的测试系统，用于测试在自动电子设计（EDA）环境下设计的待测IC器件（DUT）。基于事件的测试系统包括事件存储器，用于存储在EDA环境中直接从对于期望的IC的设计数据的模拟得到的事件数据，其中表示每个事件的事件数据形成有指示来自预定点的时间长度的时间索引，指示事件变化类型的事件类型，用于根据事件数据生成测试矢量的事件生成单元，其中由事件类型确定每个矢量的波形，并且通过累积波形的时间指数来确定波形的定时以前的事件，以及用于向DUT提供测试向量并在预定定时评估DUT的响应输出的装置。

2. 发明授权

US06404218B1 Multiple end of test signal for event based test system 失效
标题翻译：基于事件的测试系统的多端测试信号
公开(公告)号：US06404218B1
公开(公告)日：2002-06-11
申请号：US09559365
申请日：2000-04-24
申请人： Anthony Le , James Alan Turnquist , Rochit Rajsuman , Shigeru Sugamori
发明人： Anthony Le , James Alan Turnquist , Rochit Rajsuman , Shigeru Sugamori
IPC分类号： G01R3102
CPC分类号： G01R31/31937 , G01R31/31921 , G01R31/31922
摘要： An event based test system for testing semiconductor devices under test (DUT). The event based test system is freely configured to a plurality of groups of sin units where each group is able to perform test operations independently from the other. The start and end timings of the test in each group are independently made by generating multiple end of test signals. The event based test system includes a plurality of pin units to be assigned to pins of the DUT, a signal generator for generating an end of test signal for indicating an end of current test which is generated for each pin unit independently from other pin units, and a system controller for controlling an overall operation in the event based test system by communicating with each pin unit. The end of test signal for each pin unit is selected by condition specified by the system controller and the selected end of test signal is provided to the system controller and to the other pin units.
摘要翻译：用于测试被测半导体器件（DUT）的基于事件的测试系统。基于事件的测试系统被自由地配置到多个单元组，其中每个组能够彼此独立地执行测试操作。每组中的测试的开始和结束定时是通过产生测试信号的多个结果独立地进行的。基于事件的测试系统包括要分配给DUT的引脚的多个引脚单元，用于产生用于指示针对每个引脚单元独立于其它引脚单元生成的当前测试结束的测试信号结束的信号发生器，以及系统控制器，用于通过与每个引脚单元通信来控制基于事件的测试系统的整体操作。每个引脚单元的测试信号的结束由系统控制器指定的条件选择，并且所选择的测试信号的结束提供给系统控制器和其他引脚单元。

3. 发明授权

US06578169B1 Data failure memory compaction for semiconductor test system 失效
标题翻译：半导体测试系统的数据故障记忆压缩
公开(公告)号：US06578169B1
公开(公告)日：2003-06-10
申请号：US09545730
申请日：2000-04-08
申请人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
发明人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
IPC分类号： G01R3128
CPC分类号： G01R31/31935 , G11C29/56
摘要： A semiconductor test system for testing a semiconductor device under test (DUT) is able to store failure data in a data failure memory with small memory capacity. The semiconductor test system includes a pattern memory for storing pattern data therein to produce a test pattern to be supplied to the DUT, means for evaluating an output signal of the DUT and producing failure data when there is a fail therein, a data failure memory for storing the failure data, and compaction means for assigning a plurality of addresses of the pattern memory to a single address of the data failure memory in a first test operation so that failure data occurred for each group of addresses of the pattern memory is stored in a corresponding address of the data failure memory, and for executing a second test operation for only a group of addresses of the pattern memory in which the failure data is detected without an address compaction.
摘要翻译：用于测试被测半导体器件（DUT）的半导体测试系统能够将故障数据存储在具有小存储器容量的数据故障存储器中。半导体测试系统包括用于在其中存储模式数据以产生要提供给DUT的测试模式的模式存储器，用于评估DUT的输出信号的装置和当其中存在故障时产生故障数据的装置，用于存储故障数据，以及压缩装置，用于在第一测试操作中将模式存储器的多个地址分配给数据故障存储器的单个地址，使得针对模式存储器的每组地址发生的故障数据被存储在数据故障存储器的对应地址，以及仅针对其中检测到故障数据而不进行地址压缩的模式存储器的一组地址执行第二测试操作。

4. 发明授权

US06377065B1 Glitch detection for semiconductor test system 失效
标题翻译：半导体测试系统的毛刺检测
公开(公告)号：US06377065B1
公开(公告)日：2002-04-23
申请号：US09548875
申请日：2000-04-13
申请人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
发明人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
IPC分类号： G01R3126
CPC分类号： G01R31/31937 , G01R31/31922
摘要： A semiconductor test system has a glitch detection function for detecting glitches in an output signal from a device under test to accurately evaluate the device under test (DUT) . The semiconductor test system includes an event memory for storing event data, an event generator for producing test patterns, strobe signals and expected patterns based on the event data from the event memory, a pin electronics for transmitting the test pattern from the event generator to the DUT and receiving an output signal of the DUT and sampling the output signal by timings of the strobe signals, a pattern comparator for comparing sampled output data with the expected patterns, and a glitch detection unit for receiving the output signal from the DUT and detecting a glitch in the output signal by counting a number of edges in the output signal and comparing an expected number of edges.
摘要翻译：半导体测试系统具有毛刺检测功能，用于检测来自被测器件的输出信号中的毛刺，以准确地评估待测器件（DUT）。半导体测试系统包括用于存储事件数据的事件存储器，用于产生测试图案的事件发生器，用于产生来自事件存储器的事件数据的选通信号和预期模式，用于将测试模式从事件发生器发送到 DUT并接收DUT的输出信号，并通过选通信号的定时对输出信号进行采样，用于将采样输出数据与预期模式进行比较的模式比较器，以及用于从DUT接收输出信号的检测单元通过对输出信号中的边缘数进行计数并比较预期的边缘数量来在输出信号中产生毛刺。

5. 发明授权

US06668331B1 Apparatus and method for successively generating an event to establish a total delay time that is greater than can be expressed by specified data bits in an event memory 失效
标题翻译：用于连续产生事件以建立大于可由事件存储器中的指定数据位表示的总延迟时间的装置和方法
公开(公告)号：US06668331B1
公开(公告)日：2003-12-23
申请号：US09535031
申请日：2000-03-24
申请人： Glen A. Gomes , Anthony Le , James Alan Turnquist , Rochit Rajusman , Shigeru Sugamori
发明人： Glen A. Gomes , Anthony Le , James Alan Turnquist , Rochit Rajusman , Shigeru Sugamori
IPC分类号： G06F104
CPC分类号： G01R31/31922 , G01R31/31921
摘要： An apparatus and method in an event based test system for testing an electronics device under test (DUT). The apparatus includes an event memory for storing timing data and event type data of each event wherein the timing data of a current event is expressed by a delay time from an event immediately prior thereto with use of a specified number of data bits, and an additional delay time inserted in the timing data of a specified event in such a way to establish a total delay time of the current event which is longer than that can be expressed by the specified number of data bits in the event memory. The additional delay time is inserted by replicating the timing data and the event type data of the event immediately prior to the specified event.
摘要翻译：用于测试被测电子设备（DUT）的基于事件的测试系统中的装置和方法。该装置包括用于存储每个事件的定时数据和事件类型数据的事件存储器，其中当前事件的定时数据由来自使用指定数量的数据位之前的事件的延迟时间表示，并且附加延迟时间插入到指定事件的定时数据中，以建立当前事件的总延迟时间，该延迟时间长于事件存储器中指定数量的数据位可表示的总延迟时间。通过在指定事件之前复制事件的定时数据和事件类型数据来插入附加的延迟时间。

6. 发明授权

US06804620B1 Calibration method for system performance validation of automatic test equipment 失效
标题翻译：自动测试设备系统性能验证的校准方法
公开(公告)号：US06804620B1
公开(公告)日：2004-10-12
申请号：US10393876
申请日：2003-03-21
申请人： Douglas Larson , Anthony Le , Carol Qiao Tong , Rochit Rajsuman
发明人： Douglas Larson , Anthony Le , Carol Qiao Tong , Rochit Rajsuman
IPC分类号： G06F900
CPC分类号： G01R31/3191 , G01R31/31922
摘要： An ATE calibration method and system that does not require external test equipment to calibrate individual functional pins and provides balanced timing skews among the functional pins and pincards is disclosed. A functional pin in the test system is selected as a reference or “golden” pin and another is selected as a precision measurement unit (PMU). External test equipment and the reference PMU are used to measure the AC and DC characteristics of the reference pin, and any deviation represents a measurement error in the reference PMU. All functional pins in the test system can be measured against the reference pin using the reference PMU, taking into account the measurement error, without the need for external test equipment. To ensure that skews are balanced among all pins, the location of the reference pin is selected to be as close as possible to the midpoint of the functional pin range.
摘要翻译：公开了一种不需要外部测试设备来校准各个功能引脚并在功能引脚和引脚卡之间提供平衡的时序偏移的ATE校准方法和系统。选择测试系统中的功能引脚作为参考或“黄金”引脚，另一个选择为精密测量单元（PMU）。外部测试设备和参考PMU用于测量参考引脚的交流和直流特性，任何偏差表示参考PMU中的测量误差。测试系统中的所有功能引脚可以使用参考PMU测量参考引脚，同时考虑到测量误差，无需外部测试设备。为了确保所有引脚之间的偏差平衡，参考引脚的位置选择为尽可能靠近功能引脚范围的中点。

7. 发明授权

US06747447B2 Locking apparatus and loadboard assembly 失效
标题翻译：锁定装置和装载板组件
公开(公告)号：US06747447B2
公开(公告)日：2004-06-08
申请号：US10254401
申请日：2002-09-25
申请人： Niels Markert , Anthony Le , Robert Sauer , Rochit Rajsuman , Hiroki Yamoto
发明人： Niels Markert , Anthony Le , Robert Sauer , Rochit Rajsuman , Hiroki Yamoto
IPC分类号： G01R3102
CPC分类号： G01R31/2886
摘要： The present invention is directed to a locking apparatus and loadboard assembly of a semiconductor testing device apparatus. The loadboard assembly includes a printed circuit board containing a device under test and an interface board secured to the bottom of the printed circuit board. The interface board has two members with a space between them. Spacers connect the members to form apertures for contact pins on a test head. The loadboard assembly is placed on top of a locking apparatus which is mounted on the top surface of the test head. The placement of the loadboard on the locking apparatus is done according to two pins of different cross-sections that extend through two holes in the interface board and printed circuit board of the loadboard assembly. When the loadboard assembly is placed on the locking mechanism, rollers mounted on the interface board are received in cam slots of a cam member of the locking apparatus. These rollers follow the cam slots as the cam member is moved. Based on the profile of the cam slots, the loadboard assembly can be gradually lowered to achieve contact between the printed circuit board and the contact pins on the test head and to lock the interface board.
摘要翻译：本发明涉及半导体测试装置装置的锁定装置和装载板组件。装载板组件包括包含被测器件的印刷电路板和固定到印刷电路板底部的接口板。接口板有两个成员之间有空格。隔板连接构件以形成测试头上的接触针的孔。装载板组件放置在安装在测试头的顶表面上的锁定装置的顶部上。装载板在锁定装置上的布置根据延伸穿过接合板和装载板组件的印刷电路板中的两个孔的不同横截面的两个销进行。当将装载板组件放置在锁定机构上时，安装在接口板上的辊被容纳在锁定装置的凸轮构件的凸轮槽中。当凸轮构件移动时，这些滚轮跟随凸轮槽。基于凸轮槽的轮廓，可以逐渐降低装载板组件以实现印刷电路板与测试头上的接触针之间的接触并锁定接口板。

8. 发明授权

US06594609B1 Scan vector support for event based test system 失效
标题翻译：扫描向量支持基于事件的测试系统
公开(公告)号：US06594609B1
公开(公告)日：2003-07-15
申请号：US09721828
申请日：2000-11-25
申请人： Anthony Le , Rochit Rajsuman
发明人： Anthony Le , Rochit Rajsuman
IPC分类号： G01R3100
CPC分类号： G01R31/31924 , G01R31/31917
摘要： An event based test system can generate scan vectors for testing a semiconductor device of scan design without requiring a large amount of scan memory. The test system includes an event memory for storing timing data and event type data of each event where the timing data is expressed by N data bits for defining one test vector, an event generator for generating an event with use of the timing data and the event type data, and a mode change circuit provided between the event memory and the event generator for changing signal paths between a normal mode for generating the test vectors and a scan mode for generating the scan vectors. In the test system, each bit of the N data bits in the event memory defines 2N scan vectors which are provided to the event generator in a series fashion, thereby producing the 2N scan vectors at each access of the event memory.
摘要翻译：基于事件的测试系统可以生成用于测试扫描设计的半导体器件的扫描向量，而不需要大量的扫描存储器。测试系统包括事件存储器，用于存储每个事件的定时数据和事件类型数据，其中定时数据由用于定义一个测试向量的N个数据位表示，用于使用定时数据和事件来生成事件的事件发生器以及设置在事件存储器和事件发生器之间的模式改变电路，用于在用于产生测试矢量的正常模式和用于产生扫描矢量的扫描模式之间改变信号路径。在测试系统中，事件存储器中的N个数据位的每个位定义2N个扫描向量，这些扫描向量以串联方式提供给事件发生器，从而在事件存储器的每次访问期间产生2N个扫描向量。

9. 发明授权

US06226765B1 Event based test system data memory compression 失效
标题翻译：基于事件的测试系统数据存储器压缩
公开(公告)号：US06226765B1
公开(公告)日：2001-05-01
申请号：US09259402
申请日：1999-02-26
申请人： Anthony Le , James Alan Turnquist
发明人： Anthony Le , James Alan Turnquist
IPC分类号： G11C2900
CPC分类号： G01R31/31921
摘要： An event based test system for storing event data in a compressed form to reduce the size of a memory and decompressing the data to produce the events for testing a device under test (DUT). The event based test system includes a clock count memory for storing clock count data of each event wherein the clock count data is formed of one or more data words depending on the value of the integral part data, a vernier data memory for storing vernier data of each event wherein the vernier data memory stores vernier data for two or more events in the same memory location, an address sequencer for generating address data for accessing the clock count memory and the vernier data memory, a decompressor for reproducing the clock count data from the clock count memory and the vernier data from the vernier data memory corresponding to each event. The event based test system may further include an event process controller for producing an overall delay time of each event relative to a predetermined reference point based on the clock count data and vernier data from the decompressor, and a fine delay controller for generating each event based on the overall delay time to produce test signals for testing the DUT.
摘要翻译：一种基于事件的测试系统，用于以压缩形式存储事件数据，以减小存储器的大小并解压缩数据，以产生用于测试被测器件（DUT）的事件。基于事件的测试系统包括时钟计数存储器，用于存储每个事件的时钟计数数据，其中时钟计数数据由取决于整数部分数据的值的一个或多个数据字形成，用于存储游标数据的游标数据的游标数据存储器每个事件其中游标数据存储器存储相同存储器位置中的两个或更多个事件的游标数据，用于产生用于访问时钟计数存储器和游标数据存储器的地址数据的地址定序器，用于从时钟计数存储器和对应于每个事件的游标数据存储器的游标数据。基于事件的测试系统还可以包括事件处理控制器，用于基于来自解压缩器的时钟计数数据和游标数据产生相对于预定参考点的每个事件的总延迟时间，以及用于产生每个事件的精细延迟控制器在产生用于测试DUT的测试信号的总延迟时间上。

10. 发明授权

US08945933B2 Liquid chromatography-mass spectrometry methods for multiplexed detection and quantitation of free amino acids 有权
标题翻译：用于多重检测和定量游离氨基酸的液相色谱 - 质谱法
公开(公告)号：US08945933B2
公开(公告)日：2015-02-03
申请号：US12902908
申请日：2010-10-12
申请人： Anthony Le , Tina Cowan
发明人： Anthony Le , Tina Cowan
IPC分类号： G01N33/00 , G01N24/00 , G01N30/02 , G01N33/68 , G01N30/14 , G01N30/60 , G01N30/72 , G01N30/88
CPC分类号： G01N33/6806 , G01N30/14 , G01N30/6004 , G01N30/7233 , G01N33/6848 , G01N2030/8818 , G01N2500/10 , G01N2800/04 , G01N2800/52 , Y10T436/24
摘要： The present invention provides liquid chromatography-mass spectrometry methods and kits for the specific, sensitive and rapid detection as well as quantitation of free amino acids in samples following High Pressure Liquid Chromatography (HPLC) separation.
摘要翻译：本发明提供用于在高压液相色谱（HPLC）分离后样品中游离氨基酸的特异性，灵敏和快速检测以及定量游离氨基酸的液相色谱 - 质谱法和试剂盒。

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