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1. 发明申请

US20070300023A1 Method and system for terminating write commands in a hub-based memory system 有权
标题翻译：用于在基于集线器的存储器系统中终止写入命令的方法和系统
公开(公告)号：US20070300023A1
公开(公告)日：2007-12-27
申请号：US11895894
申请日：2007-08-27
申请人： Jeffrey Cronin , Douglas Larson
发明人： Jeffrey Cronin , Douglas Larson
IPC分类号： G06F12/00
CPC分类号： G06F13/423 , G06F13/1684 , G06F13/4256
摘要： A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command's write data on a downstream output port adapted to be coupled to a downstream memory hub.
摘要翻译：存储器集线器接收下游存储器命令并处理每个接收到的下游存储器命令以确定存储器命令是否包括指向存储器集线器的写入命令。当写入命令被引导到集线器以开发适于被应用于存储器件的存储器访问信号时，存储器集线器以第一模式工作。当写入命令不指向集线器以在适于耦合到下游存储器集线器的下游输出端口上提供命令的写入数据时，存储器集线器以第二模式运行。

2. 发明申请

US20060288333A1 Memory mapped lazy signal blocking 有权
公开(公告)号：US20060288333A1
公开(公告)日：2006-12-21
申请号：US11139814
申请日：2005-05-26
申请人： Paul Gootherts , Douglas Larson
发明人： Paul Gootherts , Douglas Larson
IPC分类号： G06F9/44
CPC分类号： G06F9/52
摘要： In an embodiment of the invention, a method for lazy signal blocking, includes: when a program is going to enter a critical region of code where signals will be blocked, then setting an enabled flag and marking a signal mask with signals to be blocked, wherein the enabled flag and the signal mask are in a memory address space of the program; and when the program has left the critical region of code where signals will be blocked, then clearing the enabled flag.

3. 发明申请

US20060041730A1 Memory command delay balancing in a daisy-chained memory topology 失效
标题翻译：内存命令延迟平衡菊花链内存拓扑
公开(公告)号：US20060041730A1
公开(公告)日：2006-02-23
申请号：US10922299
申请日：2004-08-19
申请人： Douglas Larson
发明人： Douglas Larson
IPC分类号： G06F13/00
CPC分类号： G11C7/22 , G06F3/0611 , G06F3/0629 , G06F3/0671 , G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. With such ability to predict command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel. A separate DIMM-specific response delay unit in the DIMM may also be programmed to provide DIMM-specific delay compensation in the response path, further allowing the memory controller to accurately ascertain the timing of receipt of a response thereat, and, hence, to better manage further processing of the response.
摘要翻译：一种菊花链存储器拓扑的方法，其中除了预测从存储器模块（DIMM）的响应的接收时间之外，存储器控制器可以有效地预测由其发送的命令何时由收件人执行 DIMM。通过在DIMM的命令延迟单元中编程DIMM特定的命令延迟，根据本公开的命令延迟平衡方法“在规范化”或“同步”命令信号在存储器通道中的所有DIMM上的执行。通过这种预测命令执行定时的能力，存储器控制器可以有效地控制菊花链式存储器通道上的所有DRAM设备（或存储器模块）的功率分布。还可以将DIMM中的单独的DIMM特定的响应延迟单元编程为在响应路径中提供特定于DIMM的延迟补偿，进一步允许存储器控制器准确地确定在那里接收响应的时间，并因此更好地管理响应的进一步处理。

4. 发明申请

US20050082238A1 Filter system 有权
标题翻译：过滤系统
公开(公告)号：US20050082238A1
公开(公告)日：2005-04-21
申请号：US10962335
申请日：2004-10-08
申请人： Douglas Larson
发明人： Douglas Larson
IPC分类号： B01D17/02
CPC分类号： B01D17/0214 , B01D17/045 , Y10S210/05
摘要： A filter system for receiving an oil-in-water emulsion contaminated with an emulsified contaminant oil, and separating the emulsified contaminant oil from the oil-in-water emulsion includes a filter media for receiving the oil-in-water emulsion and emulsified contaminant oil, having an inner filter element formed from a 95 percent single pass efficiency 48 micron (5 micron nominal) filtering material of needle punch polypropylene felt, an outer filter element formed from a 95 percent single pass efficiency 19 micron absolute filtering material of a polypropylene microfiber material and a porous spunbond polypropylene sandwiching the outer filter media. The filter element de-emulsifies the emulsified contaminant oil from the oil-in-water emulsion into the contaminant oil and the oil-in-water emulsion, separates the de-emulsified contaminant oil from the oil-in-water emulsion, coalesces the separated contaminant oil and passes both the coalesced de-emulsified contaminant oil and the oil-in-water emulsion. A first tank supports the filter element and is further configured to hold a quantity of the separated coalesced contaminant oil and the oil-in-water emulsion. The first tank has an overflow passing to a second tank. The second tank has an oil separation assembly for removing the oil-in-water emulsion from the contaminant oil and passing the oil-in-water emulsion therefrom. A method for separating the emulsified contaminant oil from the oil-in-water emulsion and recovering the oil-in-water emulsion is also disclosed.
摘要翻译：一种用于接收被乳化污染物油污染的水包油乳液的过滤系统，并且将乳化的污染物油与水包油乳液分离，包括用于接收水包油乳液和乳化污染油的过滤介质具有内部过滤元件，其由针刺聚丙烯毡的95％单通效率48微米（5微米标称）过滤材料形成，外部过滤元件由聚丙烯微纤维的95％单程效率19微米绝对过滤材料形成材料和夹带外部过滤介质的多孔纺粘聚丙烯。过滤元件将乳化的污染物油从水包油乳液中乳化成污染物油，水包油乳液将去乳化的污染物油与水包油乳液分离，将分离的污染的油并且通过聚结的去乳化的污染物油和水包油乳液。第一罐支撑过滤元件，并且进一步构造成容纳一定量的分离的聚结污染物油和水包油乳液。第一个坦克有一个溢流通过第二个坦克。第二罐具有油分离组件，用于从污染油中除去水包油乳液并从其中通过水包油乳液。还公开了一种从水包油乳液中分离乳化的污染物油并回收水包油乳液的方法。

5. 发明申请

US20090311216A1 RECOMBINANT INTERFERON-BETA WITH ENHANCED BIOLOGICAL ACTIVITY 审中-公开
标题翻译：重组干扰素与增强的生物活性
公开(公告)号：US20090311216A1
公开(公告)日：2009-12-17
申请号：US12375958
申请日：2007-07-24
申请人： Deborah Johnson-Jackson , Kenji Furuya , Isabel Zaror , Douglas Larson
发明人： Deborah Johnson-Jackson , Kenji Furuya , Isabel Zaror , Douglas Larson
IPC分类号： A61K38/21 , C07K14/565 , C12P21/02 , C12Q1/37 , C12N15/22 , C12N1/21 , C12N5/10 , A61P37/00
CPC分类号： C07K14/565
摘要： Human interferon-β protein analogs in which the asparagine at position 25, numbered in accordance with native human interferon-β, is recombinantly replaced with an aspartate residue exhibit a biological activity of human interferon-β (e.g. IFN-β 1b) at an increased level relative to IFN-β 1b. These analogs are obtained by introducing a gene coding for Asp25 IFN-β into a cell and expressing the recombinant protein. The resulting IFN-β protein analog is suitable for large scale manufacturing for incorporation in HA-containing or HA-free therapeutics for treatment of diseases including multiple sclerosis. A reduced Lys endoproteinase-C peptide map technique that produces a fingerprint profile for proteins using an enzymatic digest followed by RP-HPLC is also useful in quality control as an ID test for the IFN-β protein analog products.
摘要翻译：人类干扰素-β蛋白类似物，其中根据天然人类干扰素-β编号的第25位的天冬酰胺用天冬氨酸残基重组取代，表现出增加的人干扰素-β（例如IFN-β1b）的生物学活性水平相对于IFN-β1b。这些类似物通过将编码Asp25 IFN-β的基因导入细胞并表达重组蛋白而获得。所得的IFN-β蛋白类似物适用于大规模制造，用于掺入含HA或不含HA的治疗剂中用于治疗包括多发性硬化的疾病。使用酶消化产生RP-HPLC产生蛋白质指纹图谱的降低的Lys内蛋白酶-C肽图技术也可作为IFN-β蛋白质类似物产品的ID测试的质量控制。

6. 发明授权

US07577945B2 Memory mapped lazy signal blocking 有权
标题翻译：内存映射懒惰信号阻塞
公开(公告)号：US07577945B2
公开(公告)日：2009-08-18
申请号：US11139814
申请日：2005-05-26
申请人： Paul Gootherts , Douglas Larson
发明人： Paul Gootherts , Douglas Larson
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F9/52
摘要： In an embodiment of the invention, a method for lazy signal blocking, includes: when a program is going to enter a critical region of code where signals will be blocked, then setting an enabled flag and marking a signal mask with signals to be blocked, wherein the enabled flag and the signal mask are in a memory address space of the program; and when the program has left the critical region of code where signals will be blocked, then clearing the enabled flag.
摘要翻译：在本发明的一个实施例中，一种用于延迟信号阻塞的方法包括：当程序将要进入信号将被阻塞的关键代码区域时，然后设置使能标志并用待阻止的信号标记信号掩码，其中所述使能标志和所述信号掩码位于所述程序的存储器地址空间中; 并且当程序已经离开信号将被阻止的代码的关键区域时，清除启用的标志。

7. 发明申请

US20060271938A1 Memory mapped lazy preemption control 有权
标题翻译：内存映射懒惰抢占控制
公开(公告)号：US20060271938A1
公开(公告)日：2006-11-30
申请号：US11139840
申请日：2005-05-26
申请人： Paul Gootherts , Douglas Larson
发明人： Paul Gootherts , Douglas Larson
IPC分类号： G06F9/46
CPC分类号： G06F9/461
摘要： In an embodiment of the invention, a method for a memory-mapped lazy preemption control, the method includes: incrementing a counter value if an operating system attempts to involuntarily context switch out a thread and fails to context switch out the thread because the thread has a flag set; checking a counter value to determine a degree of abusiveness of a thread; and based upon the degree of abusiveness, determining if a voluntary contact switch out should be performed or should not be performed on the thread.
摘要翻译：在本发明的一个实施例中，一种用于存储器映射的懒惰抢占控制的方法，所述方法包括：如果操作系统试图不经意地上下文切换线程并且不能上下文切换线程，则递增计数器值，因为线程具有一个标志集检查计数器值以确定线程的滥用程度; 并且基于滥用程度，确定是否应该执行自愿接触切换或不应该在线程上执行。

8. 发明申请

US20060047990A1 System and method for data storage and transfer between two clock domains 审中-公开
标题翻译：两个时钟域之间的数据存储和传输的系统和方法
公开(公告)号：US20060047990A1
公开(公告)日：2006-03-02
申请号：US10933074
申请日：2004-09-01
申请人： Ralph James , Douglas Larson
发明人： Ralph James , Douglas Larson
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： In a memory hub system, several daisy-chained memory hubs are connected to a single memory controller. The memory hub transmitters and receivers operate in a high-speed clock domain, while the logic cores of the memory hubs operate in a low-speed clock domain. A clock domain interface advantageously provides data storage and transfer between the two clock domains without stalling the logic in the low-speed clock domain and without interrupting data movement in the high-speed clock domain.
摘要翻译：在存储器集线器系统中，几个菊花链存储器集线器连接到单个存储器控制器。存储器集线器发射器和接收器以高速时钟域工作，而存储器集线器的逻辑核心以低速时钟域工作。时钟域接口有利地在两个时钟域之间提供数据存储和传输，而不会使低速时钟域中的逻辑失速，而不会中断高速时钟域中的数据移动。

9. 发明申请

US20050177695A1 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 有权
标题翻译：用于基于集线器的存储器子系统中的双向数据总线的数据旁路的装置和方法
公开(公告)号：US20050177695A1
公开(公告)日：2005-08-11
申请号：US10773583
申请日：2004-02-05
申请人： Douglas Larson , Jeffrey Cronin
发明人： Douglas Larson , Jeffrey Cronin
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/28 , G06F12/0888 , G06F13/161
摘要： A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.
摘要翻译：存储器集线器包括用于耦合到相应的数据总线的第一和第二链路接口，耦合到第一和第二链路接口的数据路径，以及数据在第一和第二链路接口之间传送的数据路径，并且还包括写入旁路电路，将数据路径耦合到数据路径上的数据路径，并临时存储写入数据，以允许在暂时存储写入数据时通过数据路径传送读取数据。提供了一种将数据写入存储器系统中的存储器位置的方法，其包括访问存储器系统中的读取数据，向存储器系统提供写入数据，以及将写入数据耦合到寄存器以进行临时存储。在提供读取的数据之后，将写入数据重新耦合到存储器总线并写入存储器位置。

10. 发明申请

US20060048148A1 Time measurement 失效
标题翻译：时间测量
公开(公告)号：US20060048148A1
公开(公告)日：2006-03-02
申请号：US10931107
申请日：2004-08-31
申请人： Paul Gootherts , Douglas Larson
发明人： Paul Gootherts , Douglas Larson
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/5016 , G06F9/544
摘要： Systems, methods, and devices are provided for time measurement. One embodiment includes a method for measuring time on multiprocessor systems. The method includes allocating a memory space to a thread to be used to communicate with an operating system and saving a context switch count, an offset, and a scale factor, received from the operating system, in the memory space.
摘要翻译：提供系统，方法和设备进行时间测量。一个实施例包括用于在多处理器系统上测量时间的方法。该方法包括将内存空间分配给用于与操作系统进行通信的线程，并且从存储器空间中保存从操作系统接收的上下文切换计数，偏移量和比例因子。

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