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1. 发明授权

US09542671B2 Method and system to facilitate securely processing a payment for an online transaction 有权
标题翻译：方便和系统，方便安全处理在线交易的付款
公开(公告)号：US09542671B2
公开(公告)日：2017-01-10
申请号：US10844863
申请日：2004-05-12
申请人： Alan Tien , Peter Zhe Chu , Ray Hideki Tanaka , Steve S. Chen
发明人： Alan Tien , Peter Zhe Chu , Ray Hideki Tanaka , Steve S. Chen
IPC分类号： G06Q20/00 , G06Q20/04 , G06Q20/12 , G06Q20/38 , G06Q30/06
CPC分类号： G06Q20/405 , G06Q20/04 , G06Q20/12 , G06Q20/382 , G06Q20/3823 , G06Q20/3829 , G06Q30/06
摘要： A computer-implemented method, to facilitate processing a payment for an online transaction, includes, responsive to receiving secure transaction data from a merchant server, using a payment processor to generate a transaction data identifier to identify the transaction data. The payment processor communicates the transaction data identifier to the merchant server. In response to receiving a request to process a payment, including the transaction data identifier, the payment processor requests user credentials from a user. Upon receiving user credentials from the user, the payment processor verifies the user credentials. The payment processor processes the payment and generates a payment identifier to identify payment data associated with the payment. The payment processor communicates the payment identifier to the merchant server. Upon receiving a request for payment data, including the payment identifier, over a secure communication channel from the merchant server, the payment processor communicates the payment data to the merchant server.
摘要翻译：计算机实现的方法，以便于处理在线交易的支付，包括响应于从商家服务器接收安全交易数据，使用支付处理器来生成交易数据标识符以识别交易数据。支付处理器将交易数据标识符传送到商家服务器。响应于接收到处理支付的请求（包括交易数据标识符），支付处理器从用户请求用户凭证。在从用户接收用户凭证时，支付处理器验证用户凭证。支付处理器处理支付并产生支付标识符以识别与支付相关联的支付数据。支付处理器将支付标识符传送给商家服务器。在通过来自商家服务器的安全通信信道接收到包括支付标识符的支付数据请求时，支付处理器将支付数据传送到商家服务器。

2. 发明授权

US4661900A Flexible chaining in vector processor with selective use of vector registers as operand and result registers 失效
标题翻译：矢量处理器的灵活链接，可选择性地使用向量寄存器作为操作数和结果寄存器
公开(公告)号：US4661900A
公开(公告)日：1987-04-28
申请号：US858862
申请日：1986-04-30
申请人： Steve S. Chen , Alan J. Schiffleger
发明人： Steve S. Chen , Alan J. Schiffleger
IPC分类号： G06F9/30 , G06F9/38 , G06F13/18 , G06F15/17 , G06F15/78 , G06F15/347
CPC分类号： G06F9/3004 , G06F13/18 , G06F15/17 , G06F15/8084 , G06F9/30087 , G06F9/3012 , G06F9/3013 , G06F9/3885
摘要： A pair of processors are each connected to a central memory through a plurality of memory reference ports. The processors are further each connected to a plurality of shared registers which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices. A vector register design is also disclosed for use in vector processing computers, and provides that each register consist of at least two independently addressable memories, to deliver data to or accept data from a functional unit. The method of multiprocessing permits multitasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and facilitate multithreading of the operating system by permitting multiple critical code regions to be independently synchronized.
摘要翻译：一对处理器各自通过多个存储器参考端口连接到中央存储器。处理器还进一步连接到多个共享寄存器，这些共享寄存器可以由任一处理器以与处理器内操作相称的速率直接寻址。共享寄存器包括用于保存标量和地址信息的寄存器以及用于保存用于协调通过共享寄存器传送信息的信息的寄存器。提供多端口存储器并且包括冲突解决电路，其感测并优先考虑对中央存储器的冲突引用。每个CPU通过三个端口与中央存储器连接，每个端口处理可以进行的几种不同类型的存储器引用的不同的端口。提供至少一个I / O端口以由处理器在中央存储器和外围存储设备之间传送信息时共享。还公开了用于向量处理计算机中的矢量寄存器设计，并且提供每个寄存器由至少两个可独立寻址的存储器组成，以向功能单元传送数据或从功能单元接收数据。多处理方法允许多处理器中的多任务处理，其中共享寄存器允许单个作业的不同作业或相关任务的独立任务并行运行，并且通过允许多个关键代码区域被独立同步来促进操作系统的多线程化。

3. 发明授权

US5684671A Packaging architecture for a data server 失效
标题翻译：数据服务器的包装架构
公开(公告)号：US5684671A
公开(公告)日：1997-11-04
申请号：US518003
申请日：1995-08-22
申请人： Forrest B. Hobbs , Richard G. Blewett , Scott A. Wentzka , Steve S. Chen , Kitrick B. Sheets , Sheldon D. Stevens
发明人： Forrest B. Hobbs , Richard G. Blewett , Scott A. Wentzka , Steve S. Chen , Kitrick B. Sheets , Sheldon D. Stevens
IPC分类号： G06F1/18 , G11B33/12 , H05K7/16 , H05K7/18 , G06F1/16 , H05K7/14
CPC分类号： G11B33/128 , G06F1/183 , G06F1/184 , G06F1/187 , G06F1/188 , H05K7/1488
摘要： A rack-mount data server includes a housing, a plurality of data server components supported by the housing, the components including at least one peripheral storage device, a logic chassis for the data server, at least one disk drive on which the data server stores files, and at least one power supply, and a plurality of racks coupled with the housing to accommodate the data server components, the racks including a first topmost rack accommodating the at least one peripheral storage device and a second rack accommodating the logic chassis, the housing supporting the second rack underneath the first rack as the second topmost rack. The data server also includes a front door and a top door, the top door and the front door being interlockable with each other such that when the top door and the front door are in their closed positions, one of the top door and the front door locks the other of the top door and the front door in its closed position. A security system monitors the closed and/or locked status of a number of components, including the front door.
摘要翻译：机架式数据服务器包括壳体，由壳体支撑的多个数据服务器组件，所述组件包括至少一个外围存储设备，用于数据服务器的逻辑机箱，数据服务器在其上存储的至少一个磁盘驱动器文件和至少一个电源以及与外壳耦合以容纳数据服务器组件的多个机架，所述机架包括容纳至少一个外围存储设备的第一最顶端机架和容纳逻辑机箱的第二机架，将第一机架下方的第二机架支撑为第二顶部机架。数据服务器还包括前门和顶门，顶门和前门彼此互锁，使得当顶门和前门处于关闭位置时，顶门和前门之一将顶门和前门中的另一个锁在其关闭位置。安全系统监视包括前门在内的许多组件的关闭和/或锁定状态。

4. 发明授权

US5251097A Packaging architecture for a highly parallel multiprocessor system 失效
标题翻译：高度并行的多处理器系统的封装架构
公开(公告)号：US5251097A
公开(公告)日：1993-10-05
申请号：US536395
申请日：1990-06-11
申请人： Frederick J. Simmons , Steve S. Chen , Greg W. Pautsch , Michael H. Rabska , Dennis F. Girling , Douglas C. Paffel , Dan L. Massopust , Lisa Heid , Felix R. Lesmerises , Christopher J. Sperry , Edward C. Priest
发明人： Frederick J. Simmons , Steve S. Chen , Greg W. Pautsch , Michael H. Rabska , Dennis F. Girling , Douglas C. Paffel , Dan L. Massopust , Lisa Heid , Felix R. Lesmerises , Christopher J. Sperry , Edward C. Priest
IPC分类号： G06C5/02 , G06F13/40 , H02B1/20 , H05K7/20
CPC分类号： G06F13/409
摘要： The present invention includes methods and apparatus for creating a packaging architecture for a highly parallel multiprocessor system. The packaging architecture of the present invention can provide for distribution of power, cooling and interconnections at all levels of components in a highly parallel multiprocessor system, while maximizing the number of circuits per unit time within certain operational constraints of such a multiprocessor system.
摘要翻译：本发明包括用于为高度并行的多处理器系统创建包装架构的方法和装置。本发明的封装架构可以提供在高度并行的多处理器系统中的所有级别的组件上的功率，冷却和互连的分配，同时在这种多处理器系统的某些操作限制内最大化每单位时间的电路数量。

5. 外观设计

USD339603S Calculator with cutter 失效
公开(公告)号：USD339603S
公开(公告)日：1993-09-21
申请号：US851861
申请日：1992-03-16
申请人： Steve S. Chen
设计人： Steve S. Chen

6. 发明申请

US20120005685A1 Information Processing Grid and Method for High Performance and Efficient Resource Utilization 审中-公开
标题翻译：信息处理网格和高效能资源利用方法
公开(公告)号：US20120005685A1
公开(公告)日：2012-01-05
申请号：US13170894
申请日：2011-06-28
申请人： Steve S. Chen , Kitrick Sheets , Peter Marosan
发明人： Steve S. Chen , Kitrick Sheets , Peter Marosan
IPC分类号： G06F9/46
CPC分类号： G06F9/5072
摘要： System and method are proposed for intelligent assignment of submitted information processing jobs to computing resources in an information processing grid based upon real-time measurements of job behavior and predictive analysis of job throughput and computing resource consumption of the correspondingly generated workloads. The job throughput and computing resource utilization are measured and analyzed in multiple parametric dimensions. The analyzed workload may work with a job scheduling system to provide optimized job dispatchment to computing resources across the grid. Application of a parametric weighting system to the parametric dimensions makes the optimization system dynamic and flexible. Through adjustment of these parametric weights, the focus of the optimization can be adjusted dynamically to support the immediate operational goals of the system as a whole.
摘要翻译：提出了系统和方法，用于基于作业行为的实时测量和对相应产生的工作负载的计算资源消耗的预测分析，将所提交的信息处理作业智能地分配给信息处理网格中的计算资源。在多个参数维度中测量和分析作业吞吐量和计算资源利用率。分析的工作负载可能与作业调度系统一起工作，以便为跨网格的计算资源提供优化的作业调度。参数加权系统对参数尺寸的应用使得优化系统动态灵活。通过调整这些参数权重，可以动态调整优化的重点，以支持整个系统的即时操作目标。

7. 发明授权

US5208914A Method and apparatus for non-sequential resource access 失效
标题翻译：用于非顺序资源访问的方法和装置
公开(公告)号：US5208914A
公开(公告)日：1993-05-04
申请号：US535786
申请日：1990-06-11
申请人： Jimmie R. Wilson , Douglas R. Beard , Steve S. Chen , Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , Alexander A. Silbey , Brian D. Vanderwarn
发明人： Jimmie R. Wilson , Douglas R. Beard , Steve S. Chen , Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , Alexander A. Silbey , Brian D. Vanderwarn
IPC分类号： G06F9/46 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F12/00 , G06F15/16 , G06F15/173 , G06F15/177 , G06F15/78 , G06F15/80
CPC分类号： G06F15/17375 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/30094 , G06F9/3013 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for non-sequential access to shared resources in a multiple requestor system uses a variety of tags to effectively re-order the data at its destination. In simplest form, the tag directs switching logic to where in a buffer to locate another tag for direction information or where in a buffer or processor (register) to put the response associated with the tag. For example, loading data from memory requires that the requestor provide a request signal, an address, and a request tag. The request signal validates the address and request tag. The address specifies the location of the requested data in memory. The request tag specifies where to put the data when it is returned to the processor. The switching logic for the requestor includes a tag queue for storing the request tags associated with the resource requests, logic means for associating the respective request tag from the tag queue with a resource response, and means for returning the resource response and respective request tag to the requestor. The switching logic associated with the shared resource includes switching means to route the request into and out of the shared resource, control logic to correctly route the request, logic to handle multiple decision requests, and logic to store or retrieve the ultimate data entity being requested.
摘要翻译：用于在多请求者系统中非顺序访问共享资源的方法和装置使用各种标签来有效地重新排序其目的地的数据。以最简单的形式，标签将切换逻辑引导到缓冲器中的哪个位置，以定位用于方向信息的另一个标签，或者在缓冲器或处理器（寄存器）中放置与标签相关联的响应的位置。例如，从存储器加载数据要求请求者提供请求信号，地址和请求标签。请求信号验证地址和请求标签。该地址指定所请求的数据在内存中的位置。请求标签指定在将数据返回到处理器时放置数据的位置。用于请求者的切换逻辑包括用于存储与资源请求相关联的请求标签的标记队列，用于将来自标签队列的相应请求标签与资源响应相关联的逻辑装置，以及用于将资源响应和相应请求标签返回到请求者。与共享资源相关联的切换逻辑包括将请求路由到共享资源和从共享资源引出的切换装置，控制逻辑以正确路由请求，处理多个决策请求的逻辑以及存储或检索被请求的最终数据实体的逻辑。

8. 发明授权

US4901230A Computer vector multiprocessing control with multiple access memory and priority conflict resolution method 失效
标题翻译：具有多访问存储器和优先级冲突解决方法的计算机向量多处理控制
公开(公告)号：US4901230A
公开(公告)日：1990-02-13
申请号：US208809
申请日：1988-06-16
申请人： Steve S. Chen , Alan J. Schiffleger
发明人： Steve S. Chen , Alan J. Schiffleger
IPC分类号： G06F13/18 , G06F15/17 , G06F15/80 , G06F9/46 , G06F15/16
CPC分类号： G06F15/8092 , G06F13/18 , G06F15/17
摘要： A multiprocessing system and method for multiprocessing is disclosed. A pair of processors are provided, and each are connected to a central memory through a plurality of memory reference ports. The processors are further each connected to a plurality of shared registers which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices. A vector register design is also disclosed for use in vector processing computers, and provides that each register consist of at least two independently addressable memories, to deliver data to or accept data from a functional unit. The method of multiprocessing permits multitasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and facilitate multithreading of the operating system by permitting multiple critical code regions to be independently synchronized.
摘要翻译：公开了一种用于多处理的多处理系统和方法。提供一对处理器，并且每个处理器通过多个存储器参考端口连接到中央存储器。处理器还进一步连接到多个共享寄存器，这些共享寄存器可以由任一处理器以与处理器内操作相称的速率直接寻址。共享寄存器包括用于保存标量和地址信息的寄存器以及用于保存用于协调通过共享寄存器传送信息的信息的寄存器。提供多端口存储器并且包括冲突解决电路，其感测并优先考虑对中央存储器的冲突引用。每个CPU通过三个端口与中央存储器连接，每个端口处理可以进行的几种不同类型的存储器引用的不同的端口。提供至少一个I / O端口以由处理器在中央存储器和外围存储设备之间传送信息时共享。还公开了用于向量处理计算机中的矢量寄存器设计，并且提供每个寄存器由至少两个可独立寻址的存储器组成，以向功能单元传送数据或从功能单元接收数据。多处理方法允许多处理器中的多任务处理，其中共享寄存器允许单个作业的不同作业或相关任务的独立任务并行运行，并且通过允许多个关键代码区域被独立同步来促进操作系统的多线程化。

9. 发明授权

US4636942A Computer vector multiprocessing control 失效
标题翻译：计算机向量多处理控制
公开(公告)号：US4636942A
公开(公告)日：1987-01-13
申请号：US488082
申请日：1983-04-25
申请人： Steve S. Chen , Alan J. Schiffleger , Eugene R. Somdahl , Lee Higbie
发明人： Steve S. Chen , Alan J. Schiffleger , Eugene R. Somdahl , Lee Higbie
IPC分类号： G06F9/38 , G06F13/18 , G06F15/17 , G06F15/80 , G06F13/00
CPC分类号： G06F9/3877 , G06F13/18 , G06F15/17 , G06F15/8092 , G06F9/30036 , G06F9/3879 , G06F9/3887 , G06F2209/505
摘要： A multiprocessing system and method for multiprocessing is disclosed. A pair of processors are provided, and each are connected to a central memory through a plurality of memory reference ports. The processors are further each connected to the plurality of shared registers which may be directly addressed by either processor at rates commensurate with intraprocessor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices. A vector register design is also disclosed for use in vector processing computers, and provides that each register consist of at least two independently addressable memories, to deliver data to or accept data from a functional unit. The method of multiprocessing permits multitasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and facilitate multi-threading of the operating system by permitting multiple critical code regions to be independently synchronized.
摘要翻译：公开了一种用于多处理的多处理系统和方法。提供一对处理器，并且每个处理器通过多个存储器参考端口连接到中央存储器。处理器还每个连接到多个共享寄存器，这些寄存器可以由处理器以与处理器内操作相称的速率直接寻址。共享寄存器包括用于保存标量和地址信息的寄存器以及用于保存用于协调通过共享寄存器传送信息的信息的寄存器。提供多端口存储器并且包括冲突解决电路，其感测并优先考虑对中央存储器的冲突引用。每个CPU通过三个端口与中央存储器连接，每个端口处理可以进行的几种不同类型的存储器引用的不同的端口。提供至少一个I / O端口以由处理器在中央存储器和外围存储设备之间传送信息时共享。还公开了用于向量处理计算机中的矢量寄存器设计，并且提供每个寄存器由至少两个可独立寻址的存储器组成，以向功能单元传送数据或从功能单元接收数据。多处理方法允许多处理器中的多任务处理，其中共享寄存器允许单个作业的不同作业或相关任务的独立任务同时运行，并且通过允许多个关键代码区域来促进操作系统的多线程化独立同步。

10. 发明授权

US06606253B2 Scalable internet engine 有权
标题翻译：可扩展的互联网引擎
公开(公告)号：US06606253B2
公开(公告)日：2003-08-12
申请号：US10244450
申请日：2002-09-16
申请人： Russell A. Jackson , Steve S. Chen , Philip S. Smith
发明人： Russell A. Jackson , Steve S. Chen , Philip S. Smith
IPC分类号： H05K700
CPC分类号： G06F1/16
摘要： A scalable Internet engine is comprised of a large number of commercially available server boards each arranged as an engine blade in a power and space efficient cabinet. The engine blades are removably positioned in a front side of the cabinet in a vertical orientation. A through-plane in the middle of a chassis assembly within the cabinet provides common power and control peripheral signals to all engine blades. I/O signals for each engine blade are routed through apertures in the through-plane to interface cards positioned in the rear of the cabinet. The scalable engine can accommodate different types of server boards in the same chassis assembly because of a common blade carrier structure. Different types of commercially available motherboards are mounted in the common blade carrier structure that provides a uniform mechanical interface to the chassis assembly. A specially designed PCI host board that can plug into various types of motherboards has a first connector for connecting to the through plane and second connector for connecting to the interface cards. Redundant hot-swappable high-efficiency power supplies are connected to the common power signals on the through plane. The host board includes circuitry that distributes the power signals to the server board for that engine blade by emulating the ATX power management protocol. Replaceable fan trays are mounted below the engine blades to cool the engine. Preferably, the cabinet accommodates multiple rows of engine blades each in a sub-chassis that are stacked on top of each other, as well as rack mounted networks switches and disk drives.
摘要翻译：可扩展的因特网引擎由大量可商购的服务器板组成，每个服务器板在功率和空间高效的机柜中被布置为发动机叶片。发动机叶片可沿垂直方向可拆卸地定位在机柜的前侧。机柜内部的底盘组件中间的一个直通面为所有的发动机叶片提供了通用的功率和控制外围信号。每个发动机叶片的I / O信号通过通孔中的孔径传送到位于机柜后部的接口卡。可扩展引擎可以容纳同一底盘组件中不同类型的服务器主板，因为通用的刀片服务器结构。不同类型的市售主板被安装在公共叶片载体结构中，其为底盘组件提供均匀的机械接口。专门设计的PCI主板可以插入各种类型的主板，具有用于连接到通过平面的第一连接器和用于连接到接口卡的第二连接器。冗余热插拔高效电源连接到通过平面上的公共电源信号。主机板包括通过模拟ATX电源管理协议将电源信号分配到该引擎刀片服务器主板的电路。可更换的风扇托架安装在发动机叶片下方以冷却发动机。优选地，机柜容纳多个发动机叶片，每排发动机叶片分别堆叠在彼此顶部的副机架中，以及机架安装的网络开关和磁盘驱动器。

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