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1. 发明授权

US08299561B2 Shielding for high-voltage semiconductor-on-insulator devices 有权
标题翻译：高压绝缘体上半导体器件屏蔽
公开(公告)号：US08299561B2
公开(公告)日：2012-10-30
申请号：US12764244
申请日：2010-04-21
申请人： Alan B. Botula , Beth Ann Rainey , Yun Shi
发明人： Alan B. Botula , Beth Ann Rainey , Yun Shi
IPC分类号： H01L21/70 , H01L23/53 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/743 , H01L29/2003
摘要： Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.
摘要翻译：提供了在衬底中和在绝缘体上绝缘体（SOI）器件上的高压绝缘体（SOI）器件下面具有掺杂带的集成电路。在一个实施例中，本发明提供一种集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：基板; 衬底上的掩埋氧化物（BOX）层; 以及位于BOX层顶部的半导体层; 在半导体层内串联连接的多个高压（HV）器件; 在所述衬底内并在所述多个HV器件中的第一个之下的掺杂带; 以及从半导体层和BOX层延伸到掺杂带的接触。

2. 发明授权

US08890246B2 Shielding for high-voltage semiconductor-on-insulator devices 有权
标题翻译：高压绝缘体上半导体器件屏蔽
公开(公告)号：US08890246B2
公开(公告)日：2014-11-18
申请号：US13596410
申请日：2012-08-28
申请人： Alan B. Botula , Beth Ann Rainey , Yun Shi
发明人： Alan B. Botula , Beth Ann Rainey , Yun Shi
IPC分类号： H01L27/12 , H01L21/74 , H01L29/20
CPC分类号： H01L27/1203 , H01L21/743 , H01L29/2003
摘要： Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.
摘要翻译：提供了在衬底中和在绝缘体上绝缘体（SOI）器件上的高压绝缘体（SOI）器件下面具有掺杂带的集成电路。在一个实施例中，本发明提供一种集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：基板; 衬底上的掩埋氧化物（BOX）层; 以及位于BOX层顶部的半导体层; 在半导体层内串联连接的多个高压（HV）器件; 在所述衬底内并在所述多个HV器件中的第一个之下的掺杂带; 以及从半导体层和BOX层延伸到掺杂带的接触。

3. 发明申请

US20110260281A1 SHIELDING FOR HIGH-VOLTAGE SEMICONDUCTOR-ON-INSULATOR DEVICES 有权
标题翻译：用于高压半导体绝缘体器件的屏蔽
公开(公告)号：US20110260281A1
公开(公告)日：2011-10-27
申请号：US12764244
申请日：2010-04-21
申请人： Alan B. Botula , Beth Ann Rainey , Yun Shi
发明人： Alan B. Botula , Beth Ann Rainey , Yun Shi
IPC分类号： H01L27/12 , H01L23/52
CPC分类号： H01L27/1203 , H01L21/743 , H01L29/2003
摘要： Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.
摘要翻译：提供了在衬底中和在绝缘体上绝缘体（SOI）器件上的高压绝缘体（SOI）器件下面具有掺杂带的集成电路。在一个实施例中，本发明提供一种集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：基板; 衬底上的掩埋氧化物（BOX）层; 以及位于BOX层顶部的半导体层; 在半导体层内串联连接的多个高压（HV）器件; 在所述衬底内并在所述多个HV器件中的第一个之下的掺杂带; 以及从半导体层和BOX层延伸到掺杂带的接触。

4. 发明申请

US20120319229A1 SHIELDING FOR HIGH-VOLTAGE SEMICONDUCTOR-ON-INSULATOR DEVICES 有权
标题翻译：用于高压半导体绝缘体器件的屏蔽
公开(公告)号：US20120319229A1
公开(公告)日：2012-12-20
申请号：US13596410
申请日：2012-08-28
申请人： Alan B. Botula , Beth Ann Rainey , Yun Shi
发明人： Alan B. Botula , Beth Ann Rainey , Yun Shi
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/743 , H01L29/2003
摘要： Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.
摘要翻译：提供了在衬底中和在绝缘体上绝缘体（SOI）器件上的高压绝缘体（SOI）器件下面具有掺杂带的集成电路。在一个实施例中，本发明提供一种集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：基板; 衬底上的掩埋氧化物（BOX）层; 以及位于BOX层顶部的半导体层; 在半导体层内串联连接的多个高压（HV）器件; 在所述衬底内并在所述多个HV器件中的第一个之下的掺杂带; 以及从半导体层和BOX层延伸到掺杂带的接触。

5. 发明授权

US08921190B2 Field effect transistor and method of manufacture 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US08921190B2
公开(公告)日：2014-12-30
申请号：US12099175
申请日：2008-04-08
申请人： Alan B. Botula , Alvin J. Joseph , Stephen E. Luce , John J. Pekarik , Yun Shi
发明人： Alan B. Botula , Alvin J. Joseph , Stephen E. Luce , John J. Pekarik , Yun Shi
IPC分类号： H01L21/336 , H01L29/417 , H01L29/66
CPC分类号： H01L29/7834 , H01L29/0847 , H01L29/41783 , H01L29/423 , H01L29/66575
摘要： A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.
摘要翻译：提供一种半导体结构和制造方法，更具体地说，具有身体接触的场效应晶体管及其制造方法。该结构包括具有第一导电类型的凸起源极区域和延伸到器件主体的凸起源极区域下方的有源区域的器件。有源区具有不同于第一导电类型的第二导电类型。接触区域与有源区域电接触。该方法包括在器件的有源区上形成凸起的源极区域，并形成与有源区域相同的导电类型的接触区域，其中有源区域在接触区域和器件的主体之间形成接触体。

6. 发明申请

US20130134518A1 NOBLE GAS IMPLANTATION REGION IN TOP SILICON LAYER OF SEMICONDUCTOR-ON-INSULATOR SUBSTRATE 有权
标题翻译：半导体绝缘体基板的顶层硅层中的气体植入区域
公开(公告)号：US20130134518A1
公开(公告)日：2013-05-30
申请号：US13280681
申请日：2011-11-28
申请人： Alan B. Botula , William F. Clark, JR. , Richard A. Phelps , BethAnn Rainey , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , William F. Clark, JR. , Richard A. Phelps , BethAnn Rainey , Yun Shi , James A. Slinkman
IPC分类号： H01L27/088 , H01L21/302
CPC分类号： H01L21/84 , H01L27/1203
摘要： A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas.
摘要翻译：半导体结构包括绝缘体上半导体衬底，绝缘体上半导体衬底包括处理晶片，处理晶片顶部的掩埋氧化物（BOX）层和位于BOX层顶部的顶部硅层; 以及位于顶部硅层中的注入区域，该注入区域包括惰性气体。

7. 发明授权

US08299558B2 Self-aligned Schottky diode 有权
标题翻译：自对准肖特基二极管
公开(公告)号：US08299558B2
公开(公告)日：2012-10-30
申请号：US13197414
申请日：2011-08-03
申请人： Alan B. Botula , Alvin J. Joseph , Alan F. Norris , Robert M. Rassel , Yun Shi
发明人： Alan B. Botula , Alvin J. Joseph , Alan F. Norris , Robert M. Rassel , Yun Shi
IPC分类号： H01L29/66
CPC分类号： H01L29/7839 , H01L21/26586 , H01L29/665 , H01L29/66643 , H01L29/66659
摘要： A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of a first conductivity type, which is the opposite of the second conductivity type, on one side of a dummy gate electrode and a Schottky barrier structure surrounded by the doped guard ring on the other side. A Schottky barrier region may be laterally surrounded by the dummy gate electrode and the doped guard ring. The doped guard ring includes an unmetallized portion of a gate-side second-conductivity-type-doped semiconductor region having a doping of a second conductivity type. A Schottky barrier region may be laterally surrounded by a doped guard ring including a gate-side doped semiconductor region and a STI-side doped semiconductor region. Design structures for the inventive Schottky barrier diode are also provided.
摘要翻译：肖特基势垒二极管包括在绝缘体上半导体（SOI）衬底中具有第二导电类型掺杂的掺杂保护环。肖特基势垒二极管还包括在虚拟栅极电极的一侧上具有与第二导电类型相反的第一导电类型的掺杂的第一导电型掺杂半导体区域，以及被包围的肖特基势垒结构另一侧的掺杂保护环。肖特基势垒区域可以被伪栅电极和掺杂保护环横向包围。掺杂保护环包括具有第二导电类型的掺杂的栅极侧第二导电型掺杂半导体区域的未金属化部分。肖特基势垒区域可以由包括栅极掺杂半导体区域和STI侧掺杂半导体区域的掺杂保护环横向包围。还提供了用于本发明的肖特基势垒二极管的设计结构。

8. 发明授权

US08008142B2 Self-aligned Schottky diode 有权
标题翻译：自对准肖特基二极管
公开(公告)号：US08008142B2
公开(公告)日：2011-08-30
申请号：US12538213
申请日：2009-08-10
申请人： Alan B. Botula , Alvin J. Joseph , Alan D. Norris , Robert M. Rassel , Yun Shi
发明人： Alan B. Botula , Alvin J. Joseph , Alan D. Norris , Robert M. Rassel , Yun Shi
IPC分类号： H01L21/338
CPC分类号： H01L29/7839 , H01L21/26586 , H01L29/665 , H01L29/66643 , H01L29/66659
摘要： A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of a first conductivity type, which is the opposite of the second conductivity type, on one side of a dummy gate electrode and a Schottky barrier structure surrounded by the doped guard ring on the other side. A Schottky barrier region may be laterally surrounded by the dummy gate electrode and the doped guard ring. The doped guard ring includes an unmetallized portion of a gate-side second-conductivity-type-doped semiconductor region having a doping of a second conductivity type. A Schottky barrier region may be laterally surrounded by a doped guard ring including a gate-side doped semiconductor region and a STI-side doped semiconductor region. Design structures for the inventive Schottky barrier diode are also provided.
摘要翻译：肖特基势垒二极管包括在绝缘体上半导体（SOI）衬底中具有第二导电类型掺杂的掺杂保护环。肖特基势垒二极管还包括在虚拟栅极电极的一侧上具有与第二导电类型相反的第一导电类型的掺杂的第一导电型掺杂半导体区域，以及被包围的肖特基势垒结构另一侧的掺杂保护环。肖特基势垒区域可以被伪栅电极和掺杂保护环横向包围。掺杂保护环包括具有第二导电类型的掺杂的栅极侧第二导电型掺杂半导体区域的未金属化部分。肖特基势垒区域可以由包括栅极掺杂半导体区域和STI侧掺杂半导体区域的掺杂保护环横向包围。还提供了用于本发明的肖特基势垒二极管的设计结构。

9. 发明申请

US20090250772A1 FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20090250772A1
公开(公告)日：2009-10-08
申请号：US12099175
申请日：2008-04-08
申请人： Alan B. Botula , Alvin J. Joseph , Stephen E. Luce , John J. Pekarik , Yun Shi
发明人： Alan B. Botula , Alvin J. Joseph , Stephen E. Luce , John J. Pekarik , Yun Shi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7834 , H01L29/0847 , H01L29/41783 , H01L29/423 , H01L29/66575
摘要： A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.
摘要翻译：提供一种半导体结构和制造方法，更具体地说，具有身体接触的场效应晶体管及其制造方法。该结构包括具有第一导电类型的凸起源极区域和延伸到器件主体的凸起源极区域下方的有源区域的器件。有源区具有不同于第一导电类型的第二导电类型。接触区域与有源区域电接触。该方法包括在器件的有源区上形成凸起的源极区域，并形成与有源区域相同的导电类型的接触区域，其中有源区域在接触区域和器件的主体之间形成接触体。

10. 发明授权

US08916467B2 SOI radio frequency switch with enhanced signal fidelity and electrical isolation 有权
标题翻译：具有增强的信号保真度和电隔离的SOI射频开关
公开(公告)号：US08916467B2
公开(公告)日：2014-12-23
申请号：US13116396
申请日：2011-05-26
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H03K3/01 , H01L21/336 , G06F17/50 , H01L21/762 , H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76224 , H01L21/76251 , H01L21/84
摘要： A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.
摘要翻译：具有与底部半导体层相反的导电类型的掺杂接触区域设置在底部半导体层中的掩埋绝缘体层的下方。至少一个导电通孔结构从互连级金属线延伸穿过中间线（MOL）电介质层，顶部半导体层中的浅沟槽隔离结构，以及掩埋绝缘体层和掺杂接触区域。掺杂接触区域被偏置在处于或接近RF开关中的峰值电压的电压，该电压去除感应电荷层内的少数电荷载流子。少数电荷载体通过掺杂接触区域和至少一个导电通孔结构排出。诱导电荷层中的移动电荷的快速放电减少了RF开关中的谐波产生和信号失真。还提供了用于半导体结构的设计结构。

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