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1. 发明申请

US20070212861A1 LASER SURFACE ANNEALING OF ANTIMONY DOPED AMORPHIZED SEMICONDUCTOR REGION 审中-公开
标题翻译：激光表面抛光抗微生物聚合半导体器件领域
公开(公告)号：US20070212861A1
公开(公告)日：2007-09-13
申请号：US11308108
申请日：2006-03-07
申请人： Dureseti Chidambarrao , Sameer Jain , William Henson , Kern Rim
发明人： Dureseti Chidambarrao , Sameer Jain , William Henson , Kern Rim
IPC分类号： H01L21/425
CPC分类号： H01L21/26506 , H01L21/268 , H01L29/665 , H01L29/6659 , H01L29/66772 , H01L29/78621 , H01L29/78654
摘要： A sheet resistance stabilized recrystallized antimony doped region may be formed within a semiconductor substrate by annealing a corresponding antimony doped amorphized region at a temperature from about 1050° C. to about 1400° C. for a time period from about 0.1 to about 10 milliseconds. Preferably, a laser surface treatment is used. The laser surface treatment preferably uses a solid phase epitaxy. In addition, the antimony doped region may be co-doped with at least one of a phosphorus dopant and an arsenic dopant. The antimony dopant and the laser surface treatment lend sheet resistance stability that is otherwise absent when forming solely phosphorus and/or arsenic doped regions.
摘要翻译：通过在约1050℃至约1400℃的温度下退火相应的锑掺杂非晶化区域约0.1至约10毫秒的时间，可以在半导体衬底内形成薄片电阻稳定的再结晶锑掺杂区。优选地，使用激光表面处理。激光表面处理优选使用固相外延。此外，锑掺杂区域可以与磷掺杂剂和砷掺杂剂中的至少一种共掺杂。当仅形成磷和/或砷掺杂区域时，锑掺杂剂和激光表面处理提供了薄片电阻稳定性，否则不存在。

2. 发明申请

US20070123042A1 METHODS TO FORM HETEROGENEOUS SILICIDES/GERMANIDES IN CMOS TECHNOLOGY 审中-公开
标题翻译：在CMOS技术中形成异构硅氧烷/锗的方法
公开(公告)号：US20070123042A1
公开(公告)日：2007-05-31
申请号：US11164511
申请日：2005-11-28
申请人： Kern Rim , John Ellis-Monaghan , Brian Greene , William Henson , Robert Purtell , Clement Wann , Horatio Wildman
发明人： Kern Rim , John Ellis-Monaghan , Brian Greene , William Henson , Robert Purtell , Clement Wann , Horatio Wildman
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L21/84
摘要： Methods of fabricating a semiconductor structure including heterogeneous suicides or germanides located in different regions of a semiconductor structure are provided. The heterogeneous suicides or germanides are formed onto a semiconductor layer, a conductive layer or both. In accordance with the present invention, the inventive methods utilize a combination of sequential deposition of different metals and patterning to form different suicides or germanides in different regions of a semiconductor chip. The method includes providing a Si-containing or Ge layer having at least a first region and a second region; forming a first silicide or germanide on one of the first or second regions; and forming a second silicide or germanide that is compositionally different from the first silicide or germanide on the other region not including the first silicide or germanide, wherein the steps of forming the first and second suicides or germanides are performed sequentially or in a single step.
摘要翻译：提供了制造半导体结构的方法，其包括位于半导体结构的不同区域中的异质自杀或锗化物。异质自杀或锗化物形成在半导体层，导电层或两者上。根据本发明，本发明的方法利用不同金属的顺序沉积和图案化的组合以在半导体芯片的不同区域中形成不同的自杀或锗化物。该方法包括提供具有至少第一区域和第二区域的含Si或Ge层; 在所述第一或第二区域之一上形成第一硅化物或锗化物; 并且在不包括第一硅化物或锗化锗的另一区域上形成与第一硅化物或锗化物在组成上不同的第二硅化物或锗化物，其中形成第一和第二硅化物或锗化物的步骤依次进行或单步进行。

3. 发明申请

US20070254478A1 SILICIDE GATE FIELD EFFECT TRANSISTORS AND METHODS FOR FABRICATION THEREOF 失效
标题翻译：硅锗栅场效应晶体管及其制造方法
公开(公告)号：US20070254478A1
公开(公告)日：2007-11-01
申请号：US11380528
申请日：2006-04-27
申请人： Zhijiong Luo , William Henson , Christian Lavoie , Huilong Zhu
发明人： Zhijiong Luo , William Henson , Christian Lavoie , Huilong Zhu
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/28097 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method for fabricating a silicide gate field effect transistor includes masking a silicon source/drain region prior to forming the silicide gate by annealing a metal silicide forming metal layer contacting a silicon-containing gate. The silicide gate may be either a fully silicided gate or a partially silicided gate. After unmasking the source/drain region a silicide layer may be formed upon the source/drain region, and also upon the partially silicided gate. The second silicide layer and the partially silicided gate also provide a fully silicided gate.
摘要翻译：一种用于制造硅化物栅极场效应晶体管的方法，包括：在形成硅化物栅极之前，通过使接触含硅栅极的金属硅化物形成金属层退火来掩蔽硅源/漏极区。硅化物栅极可以是完全硅化的栅极或部分硅化的栅极。在去掩蔽源/漏区之后，可以在源极/漏极区上形成硅化物层，并且还可以在部分硅化物栅极上形成硅化物层。第二硅化物层和部分硅化物栅极还提供完全硅化的栅极。

4. 发明申请

US20070254423A1 HIGH PERFORMANCE STRESS-ENHANCE MOSFET AND METHOD OF MANUFACTURE 有权
标题翻译：高性能应力增强MOSFET及其制造方法
公开(公告)号：US20070254423A1
公开(公告)日：2007-11-01
申请号：US11380689
申请日：2006-04-28
申请人： Dureseti Chidambarrao , Ricardo Donaton , William Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo Donaton , William Henson , Kern Rim
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.
摘要翻译：本发明涉及半导体结构和制造方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极区域中以及PFET和NFET沟道的变化厚度的应力诱导材料。在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。

5. 发明申请

US20070254422A1 HIGH PERFORMANCE STRESS-ENHANCE MOSFET AND METHOD OF MANUFACTURE 有权
标题翻译：高性能应力增强MOSFET及其制造方法
公开(公告)号：US20070254422A1
公开(公告)日：2007-11-01
申请号：US11380688
申请日：2006-04-28
申请人： Dureseti Chidambarrao , Ricardo Donaton , William Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo Donaton , William Henson , Kern Rim
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： A semiconductor structure and method of manufacturing and more particularly a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET. The PFET region and the NFET region having a different sized gate to vary the device performance of the NFET and the PFET.
摘要翻译：一种半导体结构和制造方法，更具体地说是具有嵌入在PFET的栅极和源极/漏极区域中的应力诱导材料的CMOS器件。 PFET区域和NFET区域具有不同尺寸的栅极，以改变NFET和PFET的器件性能。

6. 发明申请

US20070228458A1 DUAL METAL INTEGRATION SCHEME BASED ON FULL SILICIDATION OF THE GATE ELECTRODE 失效
标题翻译：基于门电极全硅酸化的双金属一体化方案
公开(公告)号：US20070228458A1
公开(公告)日：2007-10-04
申请号：US11308486
申请日：2006-03-29
申请人： William Henson , Kern Rim , Jack Mandelman
发明人： William Henson , Kern Rim , Jack Mandelman
IPC分类号： H01L21/8234
CPC分类号： H01L21/823443 , H01L21/82345 , H01L21/823835 , H01L21/823842
摘要： An integration scheme that enables full silicidation (FUSI) of the nFET and pFET gate electrodes at the same time as that of the source/drain regions is provided. The FUSI of the gate electrodes eliminates the gate depletion problem that is observed with polysilicon gate electrodes. In addition, the inventive integration scheme creates different silicon thicknesses of the gate electrode just prior to silicidation. This feature of the present invention allows for fabricating nFETs and pFETs that have a band edge workfunction that is tailored for the specific device region.
摘要翻译：提供了与源极/漏极区域同时实现nFET和pFET栅电极的全硅化（FUSI）的集成方案。栅电极的FUSI消除了多晶硅栅电极观察到的栅耗尽问题。此外，本发明的集成方案刚好在硅化之前产生栅电极的不同硅厚度。本发明的该特征允许制造具有针对特定器件区域定制的带边缘功能函数的nFET和pFET。

7. 发明申请

US20070069294A1 STRESS ENGINEERING USING DUAL PAD NITRIDE WITH SELECTIVE SOI DEVICE ARCHITECTURE 有权
标题翻译：使用具有选择性SOI器件结构的双层氮化物的应力工程
公开(公告)号：US20070069294A1
公开(公告)日：2007-03-29
申请号：US11162953
申请日：2005-09-29
申请人： Dureseti Chidambarrao , William Henson , Kern Rim , William Wille
发明人： Dureseti Chidambarrao , William Henson , Kern Rim , William Wille
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/0653 , H01L29/7842
摘要： A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.
摘要翻译：描述了一种使用高应力氮化物膜与选择性绝缘体上半导体（SOI）器件结构结合的在不同导电性的MOS晶体管的沟道中应力的方法。描述了在浅沟槽隔离（STI）工艺中使用压缩和拉伸氮化物膜的方法。当将该方法应用于选择性SOI结构时，实现高应力值。

8. 发明授权

US4461469A Ball court with multiple rebound surfaces 失效
标题翻译：球场有多个反弹面
公开(公告)号：US4461469A
公开(公告)日：1984-07-24
申请号：US349623
申请日：1982-02-17
申请人： William Henson
发明人： William Henson
IPC分类号： A63C19/02 , A63B63/00
CPC分类号： A63C19/02
摘要： The disclosure concerns a court for a ballgame. A vertical wall is upstanding from a horizontal player surface. An inclined wall extends forwardly of the vertical wall. At each side end of the inclined wall, two inclined generally triangularly shaped panels are provided, each turned more toward the opposite wall. Over the top of the court is an optional ceiling. At the sides of the court, are optional side walls. At the rear of the court may be an optional rear wall.
摘要翻译：这个披露涉及一个法院进行的一场比赛。一个垂直的墙壁从水平的玩家表面是直立的。一个倾斜的墙壁从垂直的墙壁向前延伸。在倾斜壁的每个侧端设置有两个倾斜的大致三角形的面板，每个面板更靠近相对的壁。在法院的顶部是一个可选的天花板。在法院两边，是可选的侧墙。在法院的后方可能是一个可选的后墙。

9. 发明授权

US07574390B1 Revenue share interest method of financing an asset management firm 有权
标题翻译：资产管理公司融资的收益分担方法
公开(公告)号：US07574390B1
公开(公告)日：2009-08-11
申请号：US10805063
申请日：2004-03-19
申请人： William Henson , Robert Jakacki , Norton Reamer , Alexander von York
发明人： William Henson , Robert Jakacki , Norton Reamer , Alexander von York
IPC分类号： G06Q40/00
CPC分类号： G06Q40/06 , G06Q40/025
摘要： In an embodiment of a method of financing an entity, such as an asset management firm, a financing provider invests assets in the entity. The financing provider receives a revenue share interest in the financed entity. No ownership interest in the entity is given to the financing provider during the term of the revenue share interest, and no debt is used. To evaluate and price the investment, a revenue forecasting model may be used.
摘要翻译：在资产管理公司等实体的融资方式中，融资提供者将资产投资于该实体。融资提供者收到融资实体的收益份额。在收益分担利息期间，不向该融资提供者提供该实体的所有者权益，且不使用任何债务。为了评估和评估投资，可以使用收入预测模型。

10. 发明申请

US20070235759A1 CMOS process with Si gates for nFETs and SiGe gates for pFETs 审中-公开
标题翻译：用于nFET的Si栅极的CMOS工艺和用于pFET的SiGe栅极
公开(公告)号：US20070235759A1
公开(公告)日：2007-10-11
申请号：US11401672
申请日：2006-04-11
申请人： William Henson , Yaocheng Liu , Alexander Reznicek , Kern Rim , Devendra Sadana
发明人： William Henson , Yaocheng Liu , Alexander Reznicek , Kern Rim , Devendra Sadana
IPC分类号： H01L31/00
CPC分类号： H01L21/2807 , H01L21/823842
摘要： An integration scheme for providing Si gates for nFET devices and SiGe gates for pFET devices on the same semiconductor substrate is provided. The integration scheme includes first providing a material stack comprising, from bottom to top, a gate dielectric, a Si film, and a hard mask on a surface of a semiconductor substrate that includes at least one nFET device region and at least one pFET device region. Next, the hard mask is selectively removed from the material stack in the at least one pFET device region thereby exposing the Si film. The exposed Si film is then converted into a SiGe film and thereafter at least one nFET device is formed in the least one nFET device region and at least one pFET device is formed in the at least one pFET device region. In accordance with the present invention, the least one nFET device includes a Si gate and the at least one pFET includes a SiGe gate.
摘要翻译：提供了用于在同一半导体衬底上为pFET器件提供nFET器件的Si栅极和SiGe栅极的集成方案。该集成方案包括首先提供材料堆叠，其从底部到顶部包括在半导体衬底的表面上的栅极电介质，Si膜和硬掩模，其包括至少一个nFET器件区域和至少一个pFET器件区域。接下来，将硬掩模从至少一个pFET器件区域中的材料堆叠中选择性地去除，从而暴露Si膜。暴露的Si膜然后被转换成SiGe膜，此后在至少一个nFET器件区域中形成至少一个nFET器件，并且在至少一个pFET器件区域中形成至少一个pFET器件。根据本发明，至少一个nFET器件包括Si栅极，并且至少一个pFET包括SiGe栅极。

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