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1. 发明申请

US20120112273A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120112273A1
公开(公告)日：2012-05-10
申请号：US13352415
申请日：2012-01-18
申请人： Takaaki AOKI , Tomofusa Shiga
发明人： Takaaki AOKI , Tomofusa Shiga
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66734 , H01L29/7803 , H01L29/7806 , H01L29/7811 , H01L29/7828 , H01L29/8083
摘要： A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.
摘要翻译：半导体器件包括：半导体衬底; 垂直型沟槽栅极MOS晶体管; 肖特基势垒二极管; 多个沟槽具有条纹图案以将内部区域分成第一和第二分离区域; 和每个沟槽中的多晶硅膜。第一分离区域包括用于提供源极的第一导电类型区域和用于提供沟道区域的第二导电类型层。第一导电类型区域与第一沟槽相邻。第一沟槽中的多晶硅膜与栅极布线耦合。第二沟槽不与第一导电类型区域相邻。第二沟槽中的多晶硅膜与源极或栅极布线耦合。第二分离区域中的衬底与用于提供肖特基势垒的源极配线耦合。

2. 发明授权

US07800195B2 Semiconductor apparatus having temperature sensing diode 有权
标题翻译：具有温度感测二极管的半导体装置
公开(公告)号：US07800195B2
公开(公告)日：2010-09-21
申请号：US12071719
申请日：2008-02-26
申请人： Shoji Ozoe , Shoji Mizuno , Takaaki Aoki , Tomofusa Shiga
发明人： Shoji Ozoe , Shoji Mizuno , Takaaki Aoki , Tomofusa Shiga
IPC分类号： H01L31/058
CPC分类号： H01L29/945 , G01K7/015 , H01L28/40 , H01L29/92
摘要： A semiconductor apparatus is provided. The semiconductor apparatus includes a semiconductor substrate and a temperature sensing diode that is disposed on a surface part of the semiconductor substrate. A relation between a forward current flowing through the temperature sensing diode and a corresponding voltage drop across the temperature sensing diode varies with temperature. The semiconductor apparatus further includes a capacitor that is coupled with the temperature sensing diode, configured to reduce noise to act on the temperature sensing diode, and disposed such that the capacitor and the temperature sensing diode have a layered structure in a thickness direction of the semiconductor substrate.
摘要翻译：提供一种半导体装置。半导体装置包括设置在半导体衬底的表面部分上的半导体衬底和温度感测二极管。流过温度感测二极管的正向电流和温度感测二极管两端的相应电压降之间的关系随着温度而变化。半导体装置还包括与温度感测二极管耦合的电容器，其被配置为降低作用在温度感测二极管上的噪声，并且被布置为使得电容器和温度感测二极管在半导体的厚度方向上具有层状结构基质。

3. 发明授权

US09136333B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09136333B2
公开(公告)日：2015-09-15
申请号：US13352415
申请日：2012-01-18
申请人： Takaaki Aoki , Tomofusa Shiga
发明人： Takaaki Aoki , Tomofusa Shiga
IPC分类号： H01L27/088 , H01L29/06 , H01L29/66 , H01L29/78 , H01L29/808 , H01L29/423
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66734 , H01L29/7803 , H01L29/7806 , H01L29/7811 , H01L29/7828 , H01L29/8083
摘要： A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.
摘要翻译：半导体器件包括：半导体衬底; 垂直型沟槽栅极MOS晶体管; 肖特基势垒二极管; 多个沟槽具有条纹图案以将内部区域分成第一和第二分离区域; 和每个沟槽中的多晶硅膜。第一分离区域包括用于提供源极的第一导电类型区域和用于提供沟道区域的第二导电类型层。第一导电类型区域与第一沟槽相邻。第一沟槽中的多晶硅膜与栅极布线耦合。第二沟槽不与第一导电类型区域相邻。第二沟槽中的多晶硅膜与源极或栅极布线耦合。第二分离区域中的衬底与用于提供肖特基势垒的源极配线耦合。

4. 发明授权

US06974996B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06974996B2
公开(公告)日：2005-12-13
申请号：US10726590
申请日：2003-12-04
申请人： Tomofusa Shiga , Takaaki Aoki , Yoshifumi Okabe
发明人： Tomofusa Shiga , Takaaki Aoki , Yoshifumi Okabe
IPC分类号： H01L21/28 , H01L21/331 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7813 , H01L21/28185 , H01L21/28194 , H01L29/42368 , H01L29/513 , H01L29/518 , H01L29/66348 , H01L29/7397 , Y10S257/90
摘要： In a semiconductor device having a trench-gate structure in which polysilicon doped with boron is embedded in a trench, insulating film formed on the inner wall of the trench comprises ONO film, and silicon nitride film constituting the ONO film is formed to such film thickness and film quality that boron can be suppressed from passing through the silicon nitride film. Silicon oxide film is formed so that a top oxide film is thin and a bottom oxide film is thick.
摘要翻译：在具有沟槽栅结构的半导体器件中，其中掺杂有硼的多晶硅嵌入在沟槽中，形成在沟槽内壁上的绝缘膜包括ONO膜，并且构成ONO膜的氮化硅膜形成为这样的膜厚度以及能够抑制硼通过氮化硅膜的膜质量。形成氧化硅膜，使得顶部氧化膜薄，底部氧化膜厚。

5. 发明授权

US08614483B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US08614483B2
公开(公告)日：2013-12-24
申请号：US13313050
申请日：2011-12-07
申请人： Hiromitsu Tanabe , Yukio Tsuzuki , Kenji Kouno , Tomofusa Shiga
发明人： Hiromitsu Tanabe , Yukio Tsuzuki , Kenji Kouno , Tomofusa Shiga
IPC分类号： H01L29/66
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/1095 , H01L29/36 , H01L29/4236 , H01L29/66348
摘要： An insulated gate semiconductor device includes a first conductivity-type semiconductor substrate, a second conductivity-type base layer on a first surface side of the substrate, a trench dividing the base layer into channel and floating layers, and a first conductivity-type emitter region that is formed in the channel layer and in contact with the trench. The semiconductor device includes a gate insulation layer in the trench, a gate electrode on the insulation layer, an emitter electrode electrically connected to the emitter region and the floating layer, a second conductivity-type collector layer in the substrate, and a collector electrode on the collector layer. The floating layer has a lower impurity concentration than the channel layer. The floating layer has a first conductivity-type hole stopper layer located at a predetermined depth from the first surface of the substrate and at least partially spaced from the insulation layer.
摘要翻译：绝缘栅半导体器件包括第一导电型半导体衬底，在衬底的第一表面侧上的第二导电型基极层，将基极层分为沟道和浮动层的沟槽，以及第一导电型发射极区域其形成在沟道层中并与沟槽接触。半导体器件包括沟槽中的栅极绝缘层，绝缘层上的栅极电极，电连接到发射极区域和浮置层的发射极电极，衬底中的第二导电型集电极层，以及集电极电极集电极层。浮置层的杂质浓度低于沟道层。浮动层具有位于距离基板的第一表面预定深度并且至少部分地与绝缘层间隔开的第一导电型孔阻挡层。

6. 发明授权

US08154073B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08154073B2
公开(公告)日：2012-04-10
申请号：US11826206
申请日：2007-07-12
申请人： Takaaki Aoki , Tetsuo Fujii , Tomofusa Shiga
发明人： Takaaki Aoki , Tetsuo Fujii , Tomofusa Shiga
IPC分类号： H01L29/80
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66734 , H01L29/7803 , H01L29/7806 , H01L29/7811 , H01L29/7828 , H01L29/8083
摘要： A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.
摘要翻译：半导体器件包括：半导体衬底; 垂直型沟槽栅极MOS晶体管; 肖特基势垒二极管; 多个沟槽具有条纹图案以将内部区域分成第一和第二分离区域; 和每个沟槽中的多晶硅膜。第一分离区域包括用于提供源极的第一导电类型区域和用于提供沟道区域的第二导电类型层。第一导电类型区域与第一沟槽相邻。第一沟槽中的多晶硅膜与栅极布线耦合。第二沟槽不与第一导电类型区域相邻。第二沟槽中的多晶硅膜与源极或栅极布线耦合。第二分离区域中的衬底与用于提供肖特基势垒的源极配线耦合。

7. 发明授权

US07622768B2 Semiconductor device and method of manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07622768B2
公开(公告)日：2009-11-24
申请号：US11110826
申请日：2005-04-21
申请人： Takaaki Aoki , Mikimasa Suzuki , Yukio Tsuzuki , Tomofusa Shiga
发明人： Takaaki Aoki , Mikimasa Suzuki , Yukio Tsuzuki , Tomofusa Shiga
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/511 , H01L29/66348 , H01L29/7397
摘要： On the surface of a silicon nitride film, there is formed a thermal oxide film, over which a CVD oxide film is then formed to provide a silicon oxide film of two-layered structure films. Moreover, the total thickness of the two-layered structure films is set to a value from 5 nm to 30 nm. Thus, the silicon oxide film is made into the two-layered structure films of the thermal oxide film and the CVD oxide film to thereby achieve the thickness of the silicon oxide film. As a result, it is possible to prevent a Vth from being lowered by a charge trap phenomenon and to prevent the Vth from fluctuating due to the enlargement of the bird's beak length by the silicon oxide film.
摘要翻译：在氮化硅膜的表面上形成热氧化膜，然后在其上形成CVD氧化膜，以提供两层结构膜的氧化硅膜。此外，将两层结构膜的总厚度设定为5nm〜30nm的值。因此，将氧化硅膜制成热氧化膜和CVD氧化物膜的两层结构膜，从而实现氧化硅膜的厚度。结果，可以通过电荷陷阱现象防止Vth降低，并且防止由于氧化硅膜的鸟喙长度的增大而导致的Vth波动。

8. 发明申请

US20050236664A1 Semiconductor device and method of manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050236664A1
公开(公告)日：2005-10-27
申请号：US11110826
申请日：2005-04-21
申请人： Takaaki Aoki , Mikimasa Suzuki , Yukio Tsuzuki , Tomofusa Shiga
发明人： Takaaki Aoki , Mikimasa Suzuki , Yukio Tsuzuki , Tomofusa Shiga
IPC分类号： H01L29/78 , H01L21/331 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/739
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/511 , H01L29/66348 , H01L29/7397
摘要： On the surface of a silicon nitride film, there is formed a thermal oxide film, over which a CVD oxide film is then formed to provide a silicon oxide film of two-layered structure films. Moreover, the total thickness of the two-layered structure films is set to a value from 5 nm to 30 nm. Thus, the silicon oxide film is made into the two-layered structure films of the thermal oxide film and the CVD oxide film to thereby achieve the thickness of the silicon oxide film. As a result, it is possible to prevent a Vth from being lowered by a charge trap phenomenon and to prevent the Vth from fluctuating due to the enlargement of the bird's beak length by the silicon oxide film.
摘要翻译：在氮化硅膜的表面上形成热氧化膜，然后在其上形成CVD氧化膜，以提供两层结构膜的氧化硅膜。此外，将两层结构膜的总厚度设定为5nm〜30nm的值。因此，将氧化硅膜制成热氧化膜和CVD氧化物膜的两层结构膜，从而实现氧化硅膜的厚度。结果，可以通过电荷陷阱现象防止Vth降低，并且防止由于氧化硅膜的鸟喙长度的增大而导致的Vth波动。

9. 发明申请

US20120146091A1 INSULATED GATE SEMICONDUCTOR DEVICE 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US20120146091A1
公开(公告)日：2012-06-14
申请号：US13313050
申请日：2011-12-07
申请人： Hiromitsu Tanabe , Yukio Tsuzuki , Kenji Kouno , Tomofusa Shiga
发明人： Hiromitsu Tanabe , Yukio Tsuzuki , Kenji Kouno , Tomofusa Shiga
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/1095 , H01L29/36 , H01L29/4236 , H01L29/66348
摘要： An insulated gate semiconductor device includes a first conductivity-type semiconductor substrate, a second conductivity-type base layer on a first surface side of the substrate, a trench dividing the base layer into channel and floating layers, and a first conductivity-type emitter region that is formed in the channel layer and in contact with the trench. The semiconductor device includes a gate insulation layer in the trench, a gate electrode on the insulation layer, an emitter electrode electrically connected to the emitter region and the floating layer, a second conductivity-type collector layer in the substrate, and a collector electrode on the collector layer. The floating layer has a lower impurity concentration than the channel layer. The floating layer has a first conductivity-type hole stopper layer located at a predetermined depth from the first surface of the substrate and at least partially spaced from the insulation layer.
摘要翻译：绝缘栅半导体器件包括第一导电型半导体衬底，在衬底的第一表面侧上的第二导电型基极层，将基极层分为沟道和浮动层的沟槽，以及第一导电型发射极区域其形成在沟道层中并与沟槽接触。半导体器件包括沟槽中的栅极绝缘层，绝缘层上的栅极电极，电连接到发射极区域和浮置层的发射极电极，衬底中的第二导电型集电极层，以及集电极电极集电极层。浮置层的杂质浓度低于沟道层。浮动层具有位于距离基板的第一表面预定深度并且至少部分地与绝缘层间隔开的第一导电型孔阻挡层。

10. 发明授权

US07420246B2 Vertical type semiconductor device and method for manufacturing the same 有权
标题翻译：垂直型半导体器件及其制造方法
公开(公告)号：US07420246B2
公开(公告)日：2008-09-02
申请号：US11442206
申请日：2006-05-30
申请人： Shoji Ozoe , Tomofusa Shiga , Yoshifumi Okabe , Takaaki Aoki , Takeshi Fukazawa , Kimiharu Kayukawa
发明人： Shoji Ozoe , Tomofusa Shiga , Yoshifumi Okabe , Takaaki Aoki , Takeshi Fukazawa , Kimiharu Kayukawa
IPC分类号： H01L29/26
CPC分类号： H01L29/7813 , H01L21/2855 , H01L21/76838 , H01L29/1095 , H01L29/456 , H01L29/66734
摘要： A vertical type semiconductor device includes: a silicon substrate having a first surface and a second surface; a first electrode disposed on the first surface of the silicon substrate; and a second electrode disposed on the second surface of the silicon substrate. Current is capable of flowing between the first electrode and the second electrode in a vertical direction of the silicon substrate. The second surface of the silicon substrate includes a re-crystallized silicon layer. The second electrode includes an aluminum film so that the aluminum film contacts the re-crystallized silicon layer with ohmic contact.
摘要翻译：一种垂直型半导体器件包括：具有第一表面和第二表面的硅衬底; 设置在所述硅衬底的第一表面上的第一电极; 以及设置在硅衬底的第二表面上的第二电极。电流能够在硅衬底的垂直方向上在第一电极和第二电极之间流动。硅衬底的第二表面包括再结晶的硅层。第二电极包括铝膜，使得铝膜与欧姆接触的再结晶硅层接触。

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