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    • 4. 发明授权
    • Low power voltage reference circuit
    • 低功率电压参考电路
    • US6160393A
    • 2000-12-12
    • US418333
    • 1999-10-14
    • Sung-tae AhnYong-jin Jeon
    • Sung-tae AhnYong-jin Jeon
    • G05F3/24G05F3/20G05F3/26G05F3/16
    • G05F3/262
    • A bandgap voltage reference circuit according to the present invention generates a constant reference voltage and is not affected by variations in a power supply voltage and in a manufacturing process. In the bandgap voltage reference circuit, a constant voltage supply unit supplies a constant voltage, a first current mirror mirrors a first current flowing through the constant voltage supply unit to generate a second current, and a second current mirror controlled by the constant voltage from the constant voltage supply unit mirrors the second current to generate a third current and outputs the third current to an output node. A voltage reference unit is connected to the output node to provide a reference voltage to the output node. The voltage reference unit includes at least one PMOS transistor and at least one NMOS transistor which are connected to each other in series or in parallel. Ion implantation processes for determining threshold voltages of the PMOS transistor and the NMOS transistor are simultaneously performed.
    • 根据本发明的带隙电压参考电路产生恒定的参考电压,并且不受电源电压的变化和制造过程的影响。 在带隙电压基准电路中,恒定电压供给单元提供恒定电压,第一电流镜反射流过恒压电源单元的第一电流以产生第二电流,以及由来自所述恒定电压的恒定电压控制的第二电流镜 恒压电源单元镜像第二电流以产生第三电流,并将第三电流输出到输出节点。 电压参考单元连接到输出节点以向输出节点提供参考电压。 电压参考单元包括至少一个PMOS晶体管和至少一个NMOS晶体管,它们彼此串联或并联连接。 同时执行用于确定PMOS晶体管和NMOS晶体管的阈值电压的离子注入工艺。
    • 5. 发明授权
    • Device isolation method in integrated circuits
    • 集成电路中的器件隔离方法
    • US5567645A
    • 1996-10-22
    • US231705
    • 1994-04-22
    • Sung-tae AhnTai-su Park
    • Sung-tae AhnTai-su Park
    • H01L21/76H01L21/316H01L21/762
    • H01L21/76202
    • An improved method for performing a local oxidation of silicon (LOCOS) capable of forming a sufficient thickness of a field oxide film even in narrow isolation regions. After defining the isolation region, a first field oxide film is formed in the isolation region by means of a first field oxidation. A film formed of HTO, LTO or SOG, or a pre-oxide film formed of polysilicon is formed on the resultant product. Then, the film, oxide film or the pre-oxide film is removed by anisotropically etching with a dry etching process or a chemical mechanical process so as to be left only in the isolation region, which after a second field oxidation forms a second field oxide film. According to the present invention, the problems associated with the field oxide film thinning effect usually associated with the conventional LOCOS-series isolation method can be overcome by either making the isolation structure in narrow isolation regions have a total thickness which is equal to that in the wide isolation regions, or by making the former thicker than the latter.
    • 即使在狭窄的隔离区域中能够形成足够厚度的场氧化物膜的硅(LOCOS)的局部氧化的改进方法。 在限定隔离区之后,通过第一场氧化在隔离区中形成第一场氧化物膜。 在所得产物上形成由HTO,LTO或SOG形成的膜或由多晶硅形成的预氧化物膜。 然后,通过用干蚀刻工艺或化学机械工艺进行各向异性蚀刻除去膜,氧化膜或预氧化物膜,以便仅留在隔离区域中,其在第二场氧化后形成第二场氧化物 电影。 根据本发明,通常与常规LOCOS系列隔离方法相关的场氧化膜薄化效应相关的问题可以通过使狭窄隔离区域中的隔离结构的总厚度等于 或者通过使前者比后者更厚。
    • 7. 发明授权
    • Method of planarizing integrated circuits with fully recessed isolation
dielectric
    • 使用完全凹陷的隔离电介质平面化集成电路的方法
    • US6008107A
    • 1999-12-28
    • US899394
    • 1997-07-23
    • John M. PierceSung Tae Ahn
    • John M. PierceSung Tae Ahn
    • H01L21/762
    • H01L21/76229Y10S438/959
    • An integrated circuit device is fabricated upon a semi-conductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.
    • 通过首先在晶片的表面上形成停止层,在半导体晶片上制造集成电路器件。 孔通过停止层形成,并且阱形成在开口下方的半导体晶片的半导体材料中。 在装置的表面上形成介电层,其基本上填充阱并覆盖停止层。 然后将电介质层平坦化至基本上停止层的水平。 在阻挡层和半导体器件的表面之间设置PAD氧化物层。 将孔和植入物的常规薄膜氧化进入孔的侧壁进行。 使用研磨机械抛光机进行平面化处理,其中机械抛光机当遇到停止层时具有自停特征。
    • 9. 发明授权
    • Chemical resistant thermoplastic resin composition
    • 耐化学性热塑性树脂组合物
    • US07396877B2
    • 2008-07-08
    • US11248527
    • 2005-10-12
    • Sung-je ChaSung-tae AhnDong-chul KimYun-kyoung Cho
    • Sung-je ChaSung-tae AhnDong-chul KimYun-kyoung Cho
    • C08L51/04
    • C08L25/12C08L23/08C08L33/06C08L55/02C08L2666/24C08L2666/02
    • Disclosed is a resin composition comprising (A) 100 parts by weight of a base resin comprising a rubber-modified styrene-containing graft copolymer and a styrene-containing copolymer; (B) 0.5-8 parts by weight of an acrylic rubber graft copolymer resin having an average particle size of 0.1-0.5 μm; and (C) 0.5-8 parts by weight of a graft copolymer resin comprising an ethylene α-olefinic copolymer rubber having an average particle size of 0.1-0.8 μm. The thermoplastic resin composition of the present invention greatly improves chemical resistance to insulating materials, such as urethane foam, or foaming agent compounds, such as freon (CFC-11, HCFC-141b, HFC-245fa, HFC-245eb, HFC-245ca, HFC-356mffm) and cyclopentane and offers superior impact strength, whiteness and processability. It can be useful for extrusion sheets of refrigerator interiors.
    • 公开了一种树脂组合物,其包含(A)100重量份的包含橡胶改性的含苯乙烯的接枝共聚物和含苯乙烯的共聚物的基础树脂; (B)0.5-8重量份平均粒径为0.1-0.5μm的丙烯酸橡胶接枝共聚物树脂; 和(C)0.5-8重量份的包含平均粒径为0.1-0.8μm的乙烯α-烯烃共聚物橡胶的接枝共聚物树脂。 本发明的热塑性树脂组合物大大提高了对聚氨酯泡沫等绝缘材料的耐化学性,或氟利昂(CFC-11,HCFC-141b,HFC-245fa,HFC-245eb,HFC-245ca, HFC-356mffm)和环戊烷,具有优异的冲击强度,白度和加工性能。 它可用于冰箱内部的挤出片材。