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1. 发明授权

US5360753A Manufacturing method for a semiconductor isolation region 失效
标题翻译：半导体隔离区域的制造方法
公开(公告)号：US5360753A
公开(公告)日：1994-11-01
申请号：US127155
申请日：1993-09-27
申请人： Tai-seo Park , Yun-gi Kim , Dong-chul Park , Sung-tae Ahn , Byeong-yeol Kim
发明人： Tai-seo Park , Yun-gi Kim , Dong-chul Park , Sung-tae Ahn , Byeong-yeol Kim
IPC分类号： H01L21/762 , H01L21/763 , H01L21/76
CPC分类号： H01L21/76235 , H01L21/76202 , H01L21/7621 , H01L21/76221 , H01L21/763
摘要： In an element isolation method of a semiconductor device which can form an element isolation region having a flat surface without regard to the width of the element isolation region, and whose width is below the resolution limit, an insulating film having an aperture in order to define the element isolation region is formed on the semiconductor wafer, wherein an oxidizable material layer is deposited and then first spacers are formed on the sidewalls of the aperture. Then, a thermal oxide film is formed over the entire semiconductor wafer, excluding a first-spacer-formed region, and the first spacer is removed. The wafer surface is exposed to the lower part of the removed first spacer region, and then the portion of the semiconductor wafer below the exposed region is etched to thereby form a trench. After that, an element isolation region is formed by filling up the trench and removing the insulating film around tile trench. Additionally, a second spacer is formed on the sidewalls of the first spacer so as to further reduce the element isolation region. Accordingly, a highly integrated semiconductor device can be accomplished by forming an element isolation region whose size is below the resolution limit and whereby good element isolation characteristics are provided.
摘要翻译：在能够形成具有平坦表面的元件隔离区域而不考虑元件隔离区域的宽度并且其宽度低于分辨率极限的半导体器件的元件隔离方法中，具有孔径的绝缘膜以便限定元件隔离区形成在半导体晶片上，其中沉积可氧化材料层，然后在孔的侧壁上形成第一间隔物。然后，除了第一间隔物形成区域之外，在整个半导体晶片上形成热氧化膜，并且去除第一间隔物。将晶片表面暴露于去除的第一间隔区域的下部，然后蚀刻暴露区域下方的半导体晶片的部分，从而形成沟槽。之后，通过填充沟槽并去除瓷砖沟槽周围的绝缘膜来形成元件隔离区域。此外，在第一间隔件的侧壁上形成第二间隔件，以进一步减小元件隔离区域。因此，可以通过形成尺寸低于分辨率极限的元件隔离区域并由此提供良好的元件隔离特性来实现高度集成的半导体器件。

2. 发明授权

US5372950A Method for forming isolation regions in a semiconductor memory device 失效
标题翻译：在半导体存储器件中形成隔离区域的方法
公开(公告)号：US5372950A
公开(公告)日：1994-12-13
申请号：US845705
申请日：1992-03-04
申请人： Yun-gi Kim , Cheon-su Bhan , Byeong-yeol Kim
发明人： Yun-gi Kim , Cheon-su Bhan , Byeong-yeol Kim
IPC分类号： H01L21/76 , H01L21/316 , H01L21/32 , H01L21/762
CPC分类号： H01L21/76213 , H01L21/32 , Y10S438/911
摘要： A method for forming an isolation region within a semiconductor device is disclosed. A trench is first formed in a predefined isolation region of a semiconductor substrate. An oxidation blocking material is injected into the inside walls of the trench before growing a field oxide film inside the trench. Accordingly, the present invention can simplify the fabrication of isolation regions within a semiconductor device by directly implanting the oxidation blocking material at a predetermined angle into the inside walls of the trench which constitutes the isolation region. In the present invention, unlike conventional fabrication processes using spacers to prevent penetration of a field oxide film into the surface of semiconductor non-isolation regions, the need for spacers is obviated.
摘要翻译：公开了一种在半导体器件内形成隔离区域的方法。首先在半导体衬底的预定隔离区中形成沟槽。在沟槽内生长场氧化物膜之前，将氧化阻挡材料注入沟槽的内壁。因此，本发明可以通过将预定角度的氧化阻挡材料直接注入构成隔离区域的沟槽的内壁来简化半导体器件内的隔离区的制造。在本发明中，与使用间隔物以防止场氧化物膜渗透到半导体非隔离区域的表面中的常规制造方法不同，不需要间隔物。

3. 发明授权

US5252511A Isolation method in a semiconductor device 失效
标题翻译：半导体器件中的隔离方法
公开(公告)号：US5252511A
公开(公告)日：1993-10-12
申请号：US822139
申请日：1992-01-17
申请人： Cheon-su Bhan , Yun-gi Kim , Byeong-yeol Kim
发明人： Cheon-su Bhan , Yun-gi Kim , Byeong-yeol Kim
IPC分类号： H01L21/76 , H01L21/316 , H01L21/32 , H01L21/762
CPC分类号： H01L21/76202 , H01L21/32 , H01L21/76216
摘要： An isolation method in a semiconductor device which includes the steps of growing a pad oxide layer on a semiconductor substrate, depositing a polysilicon layer and a first silicon nitride layer on the pad oxide layer, removing and patterning the first silicon nitride layer to define an active region and a field region, depositing a second silicon nitride layer and a thick oxide layer, forming oxide spacers and nitride spacers, ion-implanting impurities, removing the oxide spacers, growing a field oxide layer, and sequentially removing the first silicon nitride layer, the nitride spacers, the polysilicon layer, and the pad oxide layer. This method minimizes the bird's beaks regions and increases the effective isolation distance of the device.
摘要翻译：一种半导体器件中的隔离方法，包括以下步骤：在半导体衬底上生长焊盘氧化物层，在衬垫氧化物层上沉积多晶硅层和第一氮化硅层，去除和图案化第一氮化硅层以限定活性区域和场区，沉积第二氮化硅层和厚氧化物层，形成氧化物间隔物和氮化物间隔物，离子注入杂质，去除氧化物间隔物，生长场氧化物层，以及顺序地除去第一氮化硅层，氮化物间隔物，多晶硅层和衬垫氧化物层。这种方法可以最大限度地减少鸟的喙部区域并增加设备的有效隔离距离。

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