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1. 发明授权

US07934139B2 Parallel LDPC decoder 有权
标题翻译：并行LDPC解码器
公开(公告)号：US07934139B2
公开(公告)日：2011-04-26
申请号：US11565670
申请日：2006-12-01
申请人： Alexander Andreev , Igor Vikhliantsev , Sergey Gribok
发明人： Alexander Andreev , Igor Vikhliantsev , Sergey Gribok
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1137 , H03M13/114
摘要： An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.
摘要翻译：实现迭代消息传递算法的LDPC解码器，其中改进包括流水线架构，使得解码器在列操作期间累积行操作的结果，使得不需要额外的时间和存储器来存储超过该操作的行操作的结果列操作需要。

2. 发明授权

US07656340B2 Systems and methods for pipelined analog to digital conversion 有权
标题翻译：用于流水线模数转换的系统和方法
公开(公告)号：US07656340B2
公开(公告)日：2010-02-02
申请号：US12134523
申请日：2008-06-06
申请人： Sergey Gribok , Choshu Ito , William Loh , Erik Chmelar
发明人： Sergey Gribok , Choshu Ito , William Loh , Erik Chmelar
IPC分类号： H03M1/38
CPC分类号： H03M1/182 , H03M1/002 , H03M1/004 , H03M1/361 , H03M1/367
摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit. A bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer, and the bit enable set includes one or more output bits from preceding bit periods.
摘要翻译：本发明的各种实施例提供了用于模数转换的系统和方法。例如，公开了一种流水线模数转换器，其包括两个或更多个比较器。比较器中的第一个可操作以在断言第一时钟时将模拟输入与第一参考电压进行比较，并且第二比较器可用于在断言第二时钟时将模拟输入与第二参考电压进行比较。流水线模数转换器还包括具有至少第一层多路复用器和第二层多路复用器的复用器树。第一层多路复用器接收第一比较器的输出和第二比较器的输出，并且第二层多路复用器接收从第一层多路复用器导出的输出。第二层复用器提供输出位。位使能集合用作对第一层多路复用器和第二层多路复用器的选择器输入，并且位使能集包括来自先前位周期的一个或多个输出位。

3. 发明申请

US20090309770A1 METHODS AND APPARATUS FOR PROGRAMMABLE DECODING OF A PLURALITY OF CODE TYPES 有权
标题翻译：用于可编程解码大量代码类型的方法和装置
公开(公告)号：US20090309770A1
公开(公告)日：2009-12-17
申请号：US12138920
申请日：2008-06-13
申请人： Alexander Andreev , Sergey Gribok , Oleg Izyumin , Ranko Scepanovic , Igor Vikhliantsev , Vojislav Vukovic
发明人： Alexander Andreev , Sergey Gribok , Oleg Izyumin , Ranko Scepanovic , Igor Vikhliantsev , Vojislav Vukovic
IPC分类号： H03M7/00
CPC分类号： H03M13/296 , H03M13/2725 , H03M13/6508 , H03M13/6513 , H03M13/6519 , H03M13/6525 , H03M13/6544 , H03M13/6569
摘要： Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network. The communications network can comprise, for example, a cross-bar switch and/or one or more first-in-first-out buffers.
摘要翻译：提供了用于多种代码类型的可编程解码的方法和装置。提供了一种用于解码使用多种代码类型之一编码的数据的方法，其中每种代码类型对应于通信标准。识别与数据相关联的代码类型，并将数据分配给多个可编程并行解码器。可重新配置可编程并行解码器以对使用多种代码类型中的每一种编码的数据进行解码。还提供了一种用于使用通信网络在M个并行解码器之间交织数据的方法。使用交织器表，其中交织器表中的每个条目将M个并行解码器中的一个识别为目标解码器，并将交织数据的通信网络的目标地址标识。通过将数据写入到通信网络的目标地址来交织数据。通信网络可以包括例如交叉开关和/或一个或多个先入先出缓冲器。

4. 发明申请

US20070094534A1 RRAM memory error emulation 失效
标题翻译： RRAM内存错误仿真
公开(公告)号：US20070094534A1
公开(公告)日：2007-04-26
申请号：US11257470
申请日：2005-10-24
申请人： Alexander Andreev , Vojislav Vukovic , Sergey Gribok
发明人： Alexander Andreev , Vojislav Vukovic , Sergey Gribok
IPC分类号： G06F11/00
CPC分类号： G06F11/261
摘要： A method for verifying the functionality of a repair system of configurable memory that functions to replace memory that fails predetermined tests with unused memory that passes the tests. The method includes the steps of providing a matrix comprising a plurality of reconfigurable memory blocks, providing an emulation system, generating a substitute memory block for each of the reconfigurable memory blocks utilizing the emulation system computing platform, providing a memory design that incorporates the substitute memory blocks, generating files for mapping errors into the reconfigurable memory blocks and providing a control file associated with the emulation system, and operating the emulation system to emulate the memory design.
摘要翻译：一种用于验证可配置存储器的修复系统的功能的方法，其用于替换通过测试的未使用存储器进行预定测试的存储器。该方法包括以下步骤：提供包括多个可重构存储器块的矩阵，提供仿真系统，利用仿真系统计算平台为每个可重构存储器块生成替代存储器块，提供将替代存储器生成用于将错误映射到可重构存储器块中的文件，并提供与仿真系统相关联的控制文件，以及操作仿真系统以模拟存储器设计。

5. 发明授权

US08735857B2 Via-configurable high-performance logic block architecture 有权
标题翻译：通过可配置的高性能逻辑块架构
公开(公告)号：US08735857B2
公开(公告)日：2014-05-27
申请号：US13271679
申请日：2011-10-12
申请人： Alexander Andreev , Sergey Gribok , Ranko Scepanovic
发明人： Alexander Andreev , Sergey Gribok , Ranko Scepanovic
IPC分类号： H01L27/08 , H01L47/00
CPC分类号： H03K19/17728 , H03K19/17796
摘要： A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block.
摘要翻译：通孔可配置电路块可以包含可以或可以不通过可配置通孔互连的p型和n型晶体管链。可配置的通孔也可用于将各种晶体管端子连接到接地线，电力线和/或可提供电路块外部的连接的各种端子。

6. 发明授权

US08443033B2 Variable node processing unit 失效
标题翻译：可变节点处理单元
公开(公告)号：US08443033B2
公开(公告)日：2013-05-14
申请号：US12185404
申请日：2008-08-04
申请人： Alexander Andreev , Sergey Gribok , Oleg Izyumin
发明人： Alexander Andreev , Sergey Gribok , Oleg Izyumin
IPC分类号： G06F7/50 , H03M13/00
CPC分类号： G06F7/575 , H03M13/1102 , H03M13/1111 , H03M13/1117
摘要： A variable node processing unit with N+1 inputs, having at least a first bank of two-input adders and a separate last bank of two-input adders, where the banks of adders are disposed in series.
摘要翻译：具有N + 1个输入的可变节点处理单元，其具有至少第一组双输入加法器和独立的最后一组双输入加法器，其中加法器组串联设置。

7. 发明授权

US08250129B2 Cryptographic random number generator using finite field operations 失效
标题翻译：加密随机数发生器使用有限域操作
公开(公告)号：US08250129B2
公开(公告)日：2012-08-21
申请号：US11821212
申请日：2007-06-22
申请人： Sergey Gribok , Alexander Andreev , Sergey Gashkov
发明人： Sergey Gribok , Alexander Andreev , Sergey Gashkov
IPC分类号： G06F1/02 , G06F7/58
CPC分类号： G06F7/588 , G06F7/724 , H04L9/0861
摘要： An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment.
摘要翻译：在提供快速，紧凑和密码强的随机数发生器的集成电路芯片的各种说明性实施例中提供了一种装置和方法。在一个说明性实施例中，装置包括初始随机源和与初始随机源通信连接的后处理块。后处理块被配置为从初始随机源接收信号，以将一个或多个有限场操作应用于信号以产生输出，并且在该说明性视图中通过输出通道提供基于输出的输出信号实施例。

8. 发明申请

US20110099454A1 Low Complexity LDPC Encoding Algorithm 审中-公开
标题翻译：低复杂度LDPC编码算法
公开(公告)号：US20110099454A1
公开(公告)日：2011-04-28
申请号：US12985850
申请日：2011-01-06
申请人： Sergey Gribok , Alexander Andreev , Igor Vikhliantsev
发明人： Sergey Gribok , Alexander Andreev , Igor Vikhliantsev
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： H03M13/116 , H03M13/1185
摘要： A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B′x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B′ is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form D = ( T 0 … 0 0 0 T … 0 0 … … … … … 0 0 … T 0 I I … I I ) where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.
摘要翻译：通过计算x：= Au来计算二进制源消息u，计算y：= B'x，解析p的等式Dp = y，并且并入u和p以产生编码的二进制消息v，其中A是一个仅由置换子矩阵构成的矩阵，B'是仅由循环置换子矩阵形成的矩阵，D是形式为D =（T 0 ... 0 0 0 T ... 0 0 ...... ...... 0 0 ... T 0 II ... II）其中T是双对角，循环子矩阵，I是身份子矩阵。

9. 发明授权

US07546505B2 Built in self test transport controller architecture 失效
标题翻译：内置自检传输控制器架构
公开(公告)号：US07546505B2
公开(公告)日：2009-06-09
申请号：US11557513
申请日：2006-11-08
申请人： Sergey Gribok , Alexander Andreev , Ivan Pavisic
发明人： Sergey Gribok , Alexander Andreev , Ivan Pavisic
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G11C29/16 , G11C29/34 , G11C2029/0401 , G11C2029/1204 , G11C2029/2602
摘要： A built in self test circuit in a memory matrix. Memory cells within the matrix are disposed into columns. The circuit has only one memory test controller, adapted to initiate commands and receive results. Transport controllers are paired with the columns of memory cells. The controllers receive commands from the memory test controller, test memory cells within the column, receive test results, and provide the results to the memory test controller. The transport controllers operate in three modes. A production testing mode tests the memory cells in different columns, accumulating the results for a given column with the controller associated with the column. A production testing mode retrieves the results from the controllers. A diagnostic testing mode tests memory cells within one column, while retrieving results for the column.
摘要翻译：内存自检电路在内存矩阵中。矩阵内的存储单元被排列成列。该电路只有一个内存测试控制器，适用于启动命令并接收结果。传输控制器与存储单元的列配对。控制器从存储器测试控制器接收命令，测试列内的测试存储单元，接收测试结果，并将结果提供给存储器测试控制器。运输控制器以三种模式运行。生产测试模式测试不同列中的存储单元，使用与列相关联的控制器累积给定列的结果。生产测试模式从控制器检索结果。诊断测试模式测试一列内的存储单元，同时检索列的结果。

10. 发明申请

US20060129874A1 Master controller architecture 失效
标题翻译：主控制器架构
公开(公告)号：US20060129874A1
公开(公告)日：2006-06-15
申请号：US10999720
申请日：2004-11-30
申请人： Alexandre Andreev , Sergey Gribok , Anatoli Bolotov
发明人： Alexandre Andreev , Sergey Gribok , Anatoli Bolotov
IPC分类号： G06F11/00
CPC分类号： G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72
摘要： A master controller for an RRAM subsystem. An interface communicates with at least one RRAM controller. A main control unit selects and implements test and repair operations on the RRAM subsystem through the RRAM controller. A timer determines a maximum number of test and repair operations that can be implemented within a given time. Thus, a master controller is included in the RRAM subsystem. The master controller has a relatively simple interface, and performs test and repair operations on the RRAM subsystem. The advantages of using the master controller include an elimination of additional test ports, simplification of the process of preparing the test vectors for RRAM testing, and the master controller is able to accumulate test results and initiate repairs based on those results. In this manner, the RRAM subsystem has a self-repair functionality.
摘要翻译：用于RRAM子系统的主控制器。接口与至少一个RRAM控制器通信。主控单元通过RRAM控制器对RRAM子系统进行测试和修复操作。定时器确定在给定时间内可以实现的最大测试和修复操作数。因此，主控制器包含在RRAM子系统中。主控制器具有相对简单的接口，并对RRAM子系统执行测试和修复操作。使用主控制器的优点包括消除额外的测试端口，简化了用于RRAM测试的测试向量的准备过程，并且主控制器能够根据这些结果积累测试结果并启动修复。以这种方式，RRAM子系统具有自修复功能。

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