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1. 发明授权

US5001731A Method and apparatus for eliminating clockskew race condition errors 失效
标题翻译：消除时钟竞争条件错误的方法和装置
公开(公告)号：US5001731A
公开(公告)日：1991-03-19
申请号：US415671
申请日：1989-10-02
申请人： William D. Atwell, Jr. , Richard B. Reis
发明人： William D. Atwell, Jr. , Richard B. Reis
IPC分类号： G06F1/10 , H03K5/135
CPC分类号： H03K5/135 , G06F1/10
摘要： A method and apparatus in an integrated circuit having a plurality of distinct circuit modules which eliminates undesired effects of clock skewing when a common system clock is used. The same phase of the same system clock is used by both a transmitting circuit module and a receiving circuit module when data is communicated between two circuit modules. The receiving circuit module has an input portion having a first transistor clocked by the same phase of the same system clock, a latch and a second transistor. The latch and second transistor are clocked by a complement of the same phase of the system clock.
摘要翻译：具有多个不同电路模块的集成电路中的方法和装置，其在使用公共系统时钟时消除时钟偏移的不期望的影响。当在两个电路模块之间传送数据时，发射电路模块和接收电路模块都使用相同系统时钟的相位。接收电路模块具有输入部分，该输入部分具有由相同系统时钟相同相位的时钟的第一晶体管，锁存器和第二晶体管。锁存器和第二晶体管由系统时钟相同相位的补码计时。

2. 发明授权

US5233314A Integrated charge-pump phase-locked loop circuit 失效
标题翻译：集成电荷泵锁相环电路
公开(公告)号：US5233314A
公开(公告)日：1993-08-03
申请号：US959522
申请日：1992-10-13
申请人： Mark W. McDermott , Richard B. Reis
发明人： Mark W. McDermott , Richard B. Reis
IPC分类号： H03L7/089 , H03L7/093 , H03L7/099 , H03L7/107
CPC分类号： H03L7/0898 , H03L7/0995 , H03L7/107 , H03L7/093
摘要： A variable bandwidth phase-locked loop clock generator circuit is disclosed. The PLL circuit includes a phase comparator which presents pump-up and pump-down signals, indicating the polarity of the desired frequency change. The phase comparator also generates multiple level control outputs to control the rate of the frequency change. A current source includes a reference leg having a plurality of resistors which are shorted out according to the control outputs, from which a bias signal is generated. The level of the bias signal controls current sources in the output leg of the current source to control the rate of change of the voltage applied to the voltage controlled oscillator. In addition, the bias signal also controls the slew rate of an active low-pass filter according to the desired response characteristic; the output of the filter is applied to the voltage controlled oscillator for generating the output clock signal. This construction of the PLL circuit allows for the control signals to control the rate of change both for advancing and retarding the output clock frequency, and allows for on-chip implementation of the filter components in a manner compatible with MOS technology.
摘要翻译：公开了一种可变带宽锁相环时钟发生器电路。 PLL电路包括相位比较器，其提供泵浦和抽吸信号，指示所需频率变化的极性。相位比较器还产生多个电平控制输出以控制频率变化的速率。电流源包括具有根据控制输出短路的多个电阻器的参考支线，从该电源产生偏置信号。偏置信号的电平控制电流源的输出支路中的电流源，以控制施加到压控振荡器的电压的变化率。此外，偏置信号还根据期望的响应特性来控制有源低通滤波器的转换速率; 滤波器的输出被施加到压控振荡器以产生输出时钟信号。 PLL电路的这种结构允许控制信号控制用于提前和延迟输出时钟频率的变化率，并且允许以与MOS技术兼容的方式片上实现滤波器组件。

3. 发明授权

US5878269A High speed processor for operation at reduced operating voltage 失效
标题翻译：高速处理器可在降低的工作电压下工作
公开(公告)号：US5878269A
公开(公告)日：1999-03-02
申请号：US859347
申请日：1992-03-27
申请人： John K. Eitrheim , Richard B. Reis , Steve McMahan , Lawrence H. Hudepohl , Douglas Ewing Duschatko , Tai Dinh Ngo , Jeffrey Byrne
发明人： John K. Eitrheim , Richard B. Reis , Steve McMahan , Lawrence H. Hudepohl , Douglas Ewing Duschatko , Tai Dinh Ngo , Jeffrey Byrne
IPC分类号： H03K19/017 , G06F9/00
CPC分类号： H03K19/01707
摘要： A microprocessor is implemented using sense amplifiers to replace CMOS logic circuits, in order to provide low voltage, high frequency switching. The input node of the sense amplifier is maintained at a voltage just above or just below their trip-point of one inverter in order to obtain high-speed switching. Bench mark tests have shown that a microprocessor operating at 2.7 volts may obtain a frequency of 20 MHz and while the same microprocessor may operate at 5.5 volts and 40 MHz.
摘要翻译：使用读出放大器来实现微处理器来代替CMOS逻辑电路，以便提供低电压，高频率的切换。读出放大器的输入节点保持在刚好高于或刚好低于其一个逆变器的跳变点的电压，以便获得高速切换。台式标记测试表明，以2.7伏工作的微处理器可以获得20MHz的频率，同时微处理器可以工作在5.5伏和40MHz。

4. 发明授权

US5359232A Clock multiplication circuit and method 失效
标题翻译：时钟乘法电路及方法
公开(公告)号：US5359232A
公开(公告)日：1994-10-25
申请号：US975809
申请日：1992-11-13
申请人： John K. Eitrheim , Richard B. Reis
发明人： John K. Eitrheim , Richard B. Reis
IPC分类号： G06F1/10 , H03K5/00 , H03K5/15 , H03K5/01
CPC分类号： G06F1/10 , H03K5/00006 , H03K5/15026
摘要： An integrated circuit, such as a microprocessor or math coprocessor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input signal is disclosed. A clock generator circuit comprises circuitry for detecting an active edge of an input signal, circuitry for generating a plurality of clock edges responsive to the detection of the clock signal and circuitry for inhibiting the edge generating circuitry after generation of a predetermined number of clock edges. The factor by which the input clock signal is multiplied may be set by the circuit designer, or programmably set, without impact on the circuit design. Hence, a single circuit may be used to generate clocks of various frequencies. Further, the duty cycle of the generated clock is independent of the input clock signal.
摘要翻译：公开了一种集成电路，例如微处理器或数学协处理器，其具有用于基于外部输入信号产生高频内部时钟信号的时钟发生器电路。时钟发生器电路包括用于检测输入信号的有效边沿的电路，用于响应于时钟信号的检测而生成多个时钟沿的电路和用于在产生预定数量的时钟边沿之后禁止边沿产生电路的电路的电路。输入时钟信号相乘的因素可以由电路设计者设置，或可编程设置，而不影响电路设计。因此，可以使用单个电路来产生各种频率的时钟。此外，所生成的时钟的占空比与输入时钟信号无关。

5. 发明授权

US5034636A Sense amplifier with an integral logic function 失效
标题翻译：具有积分逻辑功能的感应放大器
公开(公告)号：US5034636A
公开(公告)日：1991-07-23
申请号：US534562
申请日：1990-06-04
申请人： Richard B. Reis , James S. Golab
发明人： Richard B. Reis , James S. Golab
IPC分类号： G06F12/08 , G11C7/06 , G11C15/00 , G11C15/04
CPC分类号： G06F12/0895 , G11C7/062
摘要： A sense amplifier with an integral logic function for use in a circuit such as a tag cache portion of a microprocessor cache. In one form, the integral logic function is an exclusive-OR function. The sense amplifier senses a differential voltage developed between a differential pair of bit lines which are coupled to predetermined bit positions of a plurality of entries in a tag cache. While sensing the voltage, an exclusive-OR function is performed between the logic state of the sensed bit and a corresponding input address bit. If the input address bit matches the sensed bit, then a match signal is asserted. The value of the corresponding input address bit configures the circuit either to provide an output signal in a predetermined logic state if a true bit line signal voltage exceeds a complement bit line signal voltage, or to provide the output signal in the predetermined state if the complement bit line signal voltage exceeds the true bit line signal voltage.

6. 发明授权

US5369752A Method and apparatus for shifting data in an array of storage elements in a data processing system 失效
标题翻译：用于在数据处理系统中的存储元件阵列中的数据移位的方法和装置
公开(公告)号：US5369752A
公开(公告)日：1994-11-29
申请号：US891241
申请日：1992-06-01
申请人： Grady L. Giles , William D. Atwell, Jr. , Jesse R. Wilson , Richard B. Reis
发明人： Grady L. Giles , William D. Atwell, Jr. , Jesse R. Wilson , Richard B. Reis
IPC分类号： G11C7/10 , G11C29/32 , G06F12/02
CPC分类号： G11C7/1006 , G11C29/32
摘要： A method and apparatus for shifting data in an array of storage elements (22-37) in a data processing system (10). In one form, the present invention uses multiplexer (MUX) logic (38) and Shift Control signals to selectively couple storage elements (22-37) to latches (39-42). In this manner, data values can be serially scanned into and out of the array for test purposes without requiring a duplicate set of latches. The MUX logic 38 couples one storage element (22-37) to each latch (39-42). Then MUX logic 38 decouples those storage elements (22-37). Next, MUX logic 38 couples an adjacent storage element (22-37) to each latch (39-42). In this manner, the storage elements (22-37) in one row and the latches (39-42) mimic the functionality of a shift register.
摘要翻译：一种用于在数据处理系统（10）中的存储元件阵列（22-37）中移位数据的方法和装置。在一种形式中，本发明使用多路复用器（MUX）逻辑（38）和移位控制信号来选择性地将存储元件（22-37）耦合到锁存器（39-42）。以这种方式，数据值可以串行扫描进出阵列用于测试目的，而不需要重复的锁存器组。 MUX逻辑38将一个存储元件（22-37）耦合到每个锁存器（39-42）。然后MUX逻辑38解耦这些存储元件（22-37）。接下来，MUX逻辑38将相邻存储元件（22-37）耦合到每个锁存器（39-42）。以这种方式，一行中的存储元件（22-37）和锁存器（39-42）模拟移位寄存器的功能。

7. 发明授权

US5336939A Stable internal clock generation for an integrated circuit 失效
标题翻译：集成电路稳定的内部时钟产生
公开(公告)号：US5336939A
公开(公告)日：1994-08-09
申请号：US880550
申请日：1992-05-08
申请人： John K. Eitrheim , Richard B. Reis
发明人： John K. Eitrheim , Richard B. Reis
IPC分类号： G06F1/10 , H03K5/00 , H03K5/15 , H03K3/017 , H03K3/26
CPC分类号： H03K5/00006 , G06F1/10 , H03K5/15026
摘要： An integrated circuit, such as a microprocessor or math co-processor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input clock signal is disclosed. The clock generator circuit includes a programmable delay stage having fixed and variable portions. The fixed portion preferably includes a series of logic elements of various types (NOR, NAND, NOT, pass gates, etc.), selected to match the worst case clock phase delay and which match speed variations as a function of voltage, temperature or processing conditions. The variable portion of the delay stage selects a propagation delay by way of programmable elements (e.g., mask programmable); multiplexers may be included therein to allow selection of the delay in a test mode. The high frequency clock is generated by a circuit having a set input receiving the input clock signal and a reset input receiving the output of the programmable delay stage; as a result, the output clock signal duty cycle depends upon the propagation delay through the programmable delay stage, and not upon the duty cycle of the input clock signal. A frequency divider may also be provided to generate a lower frequency clock based on the input clock signal. In addition, the set and reset circuits may be disabled in a non-clock doubling mode, in which another frequency divider may be enabled for generating an output clock signal.
摘要翻译：公开了一种集成电路，例如微处理器或数学协处理器，其具有用于基于外部输入时钟信号产生高频内部时钟信号的时钟发生器电路。时钟发生器电路包括具有固定和可变部分的可编程延迟级。固定部分优选地包括一系列逻辑元件，其被选择为与最坏情况的时钟相位延迟匹配并且与速度变化作为电压，温度或处理的函数相匹配的各种类型的逻辑元件（NOR，NAND，NOT，通过门等）条件。延迟级的可变部分通过可编程元件（例如，可编程掩模）来选择传播延迟; 可以在其中包括多路复用器以允许在测试模式中选择延迟。高频时钟由具有接收输入时钟信号的设定输入的电路和接收可编程延迟级的输出的复位输入产生; 因此，输出时钟信号占空比取决于通过可编程延迟级的传播延迟，而不是输入时钟信号的占空比。还可以提供分频器以基于输入时钟信号产生低频时钟。此外，可以在非时钟倍增模式中禁用置位和复位电路，其中可以使能另一个分频器来产生输出时钟信号。

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