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1. 发明授权

US5878269A High speed processor for operation at reduced operating voltage 失效
标题翻译：高速处理器可在降低的工作电压下工作
公开(公告)号：US5878269A
公开(公告)日：1999-03-02
申请号：US859347
申请日：1992-03-27
申请人： John K. Eitrheim , Richard B. Reis , Steve McMahan , Lawrence H. Hudepohl , Douglas Ewing Duschatko , Tai Dinh Ngo , Jeffrey Byrne
发明人： John K. Eitrheim , Richard B. Reis , Steve McMahan , Lawrence H. Hudepohl , Douglas Ewing Duschatko , Tai Dinh Ngo , Jeffrey Byrne
IPC分类号： H03K19/017 , G06F9/00
CPC分类号： H03K19/01707
摘要： A microprocessor is implemented using sense amplifiers to replace CMOS logic circuits, in order to provide low voltage, high frequency switching. The input node of the sense amplifier is maintained at a voltage just above or just below their trip-point of one inverter in order to obtain high-speed switching. Bench mark tests have shown that a microprocessor operating at 2.7 volts may obtain a frequency of 20 MHz and while the same microprocessor may operate at 5.5 volts and 40 MHz.
摘要翻译：使用读出放大器来实现微处理器来代替CMOS逻辑电路，以便提供低电压，高频率的切换。读出放大器的输入节点保持在刚好高于或刚好低于其一个逆变器的跳变点的电压，以便获得高速切换。台式标记测试表明，以2.7伏工作的微处理器可以获得20MHz的频率，同时微处理器可以工作在5.5伏和40MHz。

2. 发明申请

US20100305857A1 Method and System for Visual Collision Detection and Estimation 审中-公开
标题翻译：视觉碰撞检测与估计方法与系统
公开(公告)号：US20100305857A1
公开(公告)日：2010-12-02
申请号：US12776202
申请日：2010-05-07
申请人： Jeffrey Byrne , Raman K. Mehra
发明人： Jeffrey Byrne , Raman K. Mehra
IPC分类号： G08G1/16 , G06K9/00
CPC分类号： G06T7/73 , G06T2207/30248
摘要： Collision detection and estimation from a monocular visual sensor is an important enabling technology for safe navigation of small or micro air vehicles in near earth flight. In this paper, we introduce a new approach called expansion segmentation, which simultaneously detects “collision danger regions” of significant positive divergence in inertial aided video, and estimates maximum likelihood time to collision (TTC) in a correspondenceless framework within the danger regions. This approach was motivated from a literature review which showed that existing approaches make strong assumptions about scene structure or camera motion, or pose collision detection without determining obstacle boundaries, both of which limit the operational envelope of a deployable system. Expansion segmentation is based on a new formulation of 6-DOF inertial aided TTC estimation, and a new derivation of a first order TTC uncertainty model due to subpixel quantization error and epipolar geometry uncertainty. Proof of concept results are shown in a custom designed urban flight simulator and on operational flight data from a small air vehicle.
摘要翻译：来自单目视觉传感器的碰撞检测和估计是近地飞行中小型或微型飞行器的安全导航的重要使能技术。在本文中，我们引入了一种称为扩展分段的新方法，其同时检测惯性辅助视频中的显着正偏差的“碰撞危险区域”，并估计危险区域内的无关框架中的最大碰撞时间（TTC）。这种方法是从文献综述中得出的，这表明现有方法对场景结构或摄像机运动做出了强烈的假设，或者在不确定障碍物边界的情况下进行碰撞检测，这两者都限制了可部署系统的运行范围。扩展分割基于6自由度惯性辅助TTC估计的新公式，以及由于子像素量化误差和对极几何不确定性引起的一阶TTC不确定性模型的新推导。概念证明结果显示在定制设计的城市飞行模拟器和来自小型飞行器的操作飞行数据上。

3. 发明申请

US20210219529A1 Magnetic Braking System 有权
公开(公告)号：US20210219529A1
公开(公告)日：2021-07-22
申请号：US16748444
申请日：2020-01-21
申请人： Jeffrey Byrne
发明人： Jeffrey Byrne
IPC分类号： A01K89/0155
摘要： In some embodiments, the system for magnetic braking in fishing reels includes a fishing reel including a spool, a lever, a rotor, and a movable slider device. The rotor includes a plurality of spaced-apart holes and a plurality of magnets in the plurality of holes. The slider device includes a first sheet, a second sheet and a third sheet. Each of the second sheet and the third sheet include a magnet in a hole. The slider device is movable between a first position and a second position, where the first position is farther apart from a center of the rotor. The interactions between the one or more magnets of the movable slider device and the plurality of the magnets of the rotor cause the rotor to brake when the movable slider device is at the second position.

4. 发明申请

US20050071730A1 Continuous self-verify of configuration memory in programmable logic devices 审中-公开
标题翻译：可编程逻辑器件中配置存储器的连续自校验
公开(公告)号：US20050071730A1
公开(公告)日：2005-03-31
申请号：US10676494
申请日：2003-09-30
申请人： Mark Moyer , Jeffrey Byrne
发明人： Mark Moyer , Jeffrey Byrne
IPC分类号： G06F11/10 , G11C16/20 , H03M13/09 , H03M13/00 , G11C29/00
CPC分类号： H03K19/17764 , G06F11/1004 , G11C16/20 , G11C2029/4402 , H03M13/09
摘要： A programmable logic device (PLD) such as an FPGA or CPLD is supplementally configured to verify the integrity of its configuration data during operation of the device. The programmable logic device includes a checksum calculation engine to calculate a checksum based upon the configuration data. A checksum comparator compares the calculated checksum to a previously-calculated checksum to verify the integrity of the configuration data.
摘要翻译：诸如FPGA或CPLD的可编程逻辑器件（PLD）被补充配置为在器件的操作期间验证其配置数据的完整性。可编程逻辑器件包括基于配置数据计算校验和的校验和计算引擎。校验和比较器将计算的校验和与先前计算的校验和进行比较，以验证配置数据的完整性。

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