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1. 发明授权

US5841195A Semiconductor contact via structure 失效
标题翻译：半导体接触通孔结构
公开(公告)号：US5841195A
公开(公告)日：1998-11-24
申请号：US448703
申请日：1995-05-24
申请人： Yih-Shung Lin , Lun-Tseng Lu , Fu-Tai Liou , Che-Chia Wei , John Leonard Walters
发明人： Yih-Shung Lin , Lun-Tseng Lu , Fu-Tai Liou , Che-Chia Wei , John Leonard Walters
IPC分类号： H01L21/28 , H01L21/768 , H01L23/485 , H01L23/522 , H01L23/532
CPC分类号： H01L23/485 , H01L21/76804 , H01L2924/0002
摘要： A method is provided for forming contact via in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.
摘要翻译：提供了一种用于在集成电路中形成接触通孔的方法。首先，在集成电路中的绝缘层上形成第一缓冲层。第一缓冲层具有与绝缘层不同的蚀刻速率。然后在第一缓冲层上形成第二缓冲层，其中第二缓冲层具有比第一缓冲层快的蚀刻速率。执行各向同性蚀刻以产生通过第二缓冲层和第一缓冲层的一部分的开口。因为第二缓冲层比第一缓冲层蚀刻更快，所以可以控制开口的侧壁的倾斜。然后进行各向异性蚀刻以完成接触通孔的形成。

2. 发明授权

US5500557A Structure and method for fabricating integrated circuits 失效
标题翻译：集成电路制造的结构和方法
公开(公告)号：US5500557A
公开(公告)日：1996-03-19
申请号：US126673
申请日：1993-09-24
申请人： Tsiu C. Chan , Frank R. Bryant , Lun-Tseng Lu , Che-Chia Wei
发明人： Tsiu C. Chan , Frank R. Bryant , Lun-Tseng Lu , Che-Chia Wei
IPC分类号： H01L23/528 , H01L23/532 , H01L23/48
CPC分类号： H01L23/5283 , H01L23/53271 , H01L2924/0002
摘要： A structure and method for fabricating integrated circuits which provides for the detection of residual conductive material. A first conductive layer is deposited over the integrated circuit and patterned to define a first interconnect layer. An insulating layer is then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during patterning of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.
摘要翻译：用于制造集成电路的结构和方法，其提供残留导电材料的检测。第一导电层沉积在集成电路上并被图案化以限定第一互连层。然后在集成电路上形成绝缘层。然后沉积和图案化第二导电层以限定第二互连层。当第二导电层的部分保持与第一互连层的垂直侧壁相邻时，可以在图案化第二互连层期间形成剩余的导电材料。为了使残留的导电材料更易于检测，通过将杂质注入集成电路或用难熔金属硅化残留的导电材料来增加剩余导电材料的导电性。

3. 发明授权

US5485035A Method for planarization of an integrated circuit 失效
标题翻译：集成电路平面化方法
公开(公告)号：US5485035A
公开(公告)日：1996-01-16
申请号：US174430
申请日：1993-12-28
申请人： Yih-Shung Lin , Kuei-Wu Huang , Lun-Tseng Lu
发明人： Yih-Shung Lin , Kuei-Wu Huang , Lun-Tseng Lu
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L23/48 , H01L29/46 , H01L29/54 , H01L29/62
CPC分类号： H01L21/76819
摘要： A method for planarization of an integrated circuit. After a first conducting layer is deposited and patterned, a first insulating layer is deposited over the device. A planarizing layer is then deposited over the integrated circuit and etched back. Portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the device. A second insulating layer is then deposited over the integrated circuit, followed by a third insulating layer. A contact via is formed through the layers to expose a portion of the first conducting layer. A second conducting layer can now be deposited and patterned on the device to make electrical contact with the first conducting layer.
摘要翻译：一种集成电路的平坦化方法。在沉积和图案化第一导电层之后，在器件上沉积第一绝缘层。然后将平坦化层沉积在集成电路上并被回蚀刻。平坦化层的一部分可以保留在第一绝缘层的下部形貌区域中，以使器件的表面平坦化。然后在集成电路上沉积第二绝缘层，随后沉积第三绝缘层。通过这些层形成接触通孔以暴露第一导电层的一部分。现在可以在器件上沉积和图案化第二导电层以与第一导电层电接触。

4. 发明授权

US5595935A Method for forming interconnect in integrated circuits 失效
标题翻译：在集成电路中形成互连的方法
公开(公告)号：US5595935A
公开(公告)日：1997-01-21
申请号：US418191
申请日：1995-04-07
申请人： Tsiu C. Chan , Frank R. Bryant , Lun-Tseng Lu , Che-Chia Wei
发明人： Tsiu C. Chan , Frank R. Bryant , Lun-Tseng Lu , Che-Chia Wei
IPC分类号： H01L23/528 , H01L23/532 , H01L21/28
CPC分类号： H01L23/5283 , H01L23/53271 , H01L2924/0002
摘要： A structure and method for fabricating intergrated circuit which provides for the detection of residual conductive material. A first conductive layer is deposited over the intergrated circuit and patterned to define a first interconnect layer. An insulating layer in then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during pattering of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.
摘要翻译：用于制造集成电路的结构和方法，其提供残留导电材料的检测。第一导电层沉积在集成电路上并被图案化以限定第一互连层。然后形成在集成电路上的绝缘层。然后沉积和图案化第二导电层以限定第二互连层。当第二导电层的部分保持与第一互连层的垂直侧壁相邻时，可以在第二互连层的图形期间形成剩余的导电材料。为了使残留的导电材料更易于检测，通过将杂质注入集成电路或用难熔金属硅化残留的导电材料来增加剩余导电材料的导电性。

5. 发明授权

US5246883A Semiconductor contact via structure and method 失效
标题翻译：半导体与结构与方法联系
公开(公告)号：US5246883A
公开(公告)日：1993-09-21
申请号：US832088
申请日：1992-02-06
申请人： Yih-Shung Lin , Lun-Tseng Lu , Fu-Tai Liou , Che-Chia Wei , John L. Walters
发明人： Yih-Shung Lin , Lun-Tseng Lu , Fu-Tai Liou , Che-Chia Wei , John L. Walters
IPC分类号： H01L21/28 , H01L21/768 , H01L23/485 , H01L23/522
CPC分类号： H01L23/485 , H01L21/76804 , H01L2924/0002
摘要： A method is provided for forming contact vias in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.

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