专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5500557A Structure and method for fabricating integrated circuits 失效
标题翻译：集成电路制造的结构和方法
公开(公告)号：US5500557A
公开(公告)日：1996-03-19
申请号：US126673
申请日：1993-09-24
申请人： Tsiu C. Chan , Frank R. Bryant , Lun-Tseng Lu , Che-Chia Wei
发明人： Tsiu C. Chan , Frank R. Bryant , Lun-Tseng Lu , Che-Chia Wei
IPC分类号： H01L23/528 , H01L23/532 , H01L23/48
CPC分类号： H01L23/5283 , H01L23/53271 , H01L2924/0002
摘要： A structure and method for fabricating integrated circuits which provides for the detection of residual conductive material. A first conductive layer is deposited over the integrated circuit and patterned to define a first interconnect layer. An insulating layer is then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during patterning of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.
摘要翻译：用于制造集成电路的结构和方法，其提供残留导电材料的检测。第一导电层沉积在集成电路上并被图案化以限定第一互连层。然后在集成电路上形成绝缘层。然后沉积和图案化第二导电层以限定第二互连层。当第二导电层的部分保持与第一互连层的垂直侧壁相邻时，可以在图案化第二互连层期间形成剩余的导电材料。为了使残留的导电材料更易于检测，通过将杂质注入集成电路或用难熔金属硅化残留的导电材料来增加剩余导电材料的导电性。

2. 发明授权

US5595935A Method for forming interconnect in integrated circuits 失效
标题翻译：在集成电路中形成互连的方法
公开(公告)号：US5595935A
公开(公告)日：1997-01-21
申请号：US418191
申请日：1995-04-07
申请人： Tsiu C. Chan , Frank R. Bryant , Lun-Tseng Lu , Che-Chia Wei
发明人： Tsiu C. Chan , Frank R. Bryant , Lun-Tseng Lu , Che-Chia Wei
IPC分类号： H01L23/528 , H01L23/532 , H01L21/28
CPC分类号： H01L23/5283 , H01L23/53271 , H01L2924/0002
摘要： A structure and method for fabricating intergrated circuit which provides for the detection of residual conductive material. A first conductive layer is deposited over the intergrated circuit and patterned to define a first interconnect layer. An insulating layer in then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during pattering of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.
摘要翻译：用于制造集成电路的结构和方法，其提供残留导电材料的检测。第一导电层沉积在集成电路上并被图案化以限定第一互连层。然后形成在集成电路上的绝缘层。然后沉积和图案化第二导电层以限定第二互连层。当第二导电层的部分保持与第一互连层的垂直侧壁相邻时，可以在第二互连层的图形期间形成剩余的导电材料。为了使残留的导电材料更易于检测，通过将杂质注入集成电路或用难熔金属硅化残留的导电材料来增加剩余导电材料的导电性。

3. 发明授权

US5894160A Method of forming a landing pad structure in an integrated circuit 失效
公开(公告)号：US5894160A
公开(公告)日：1999-04-13
申请号：US725621
申请日：1996-10-03
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/02 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.

4. 发明授权

US5489797A Local interconnect structure 失效
标题翻译：本地互连结构
公开(公告)号：US5489797A
公开(公告)日：1996-02-06
申请号：US420353
申请日：1995-04-11
申请人： Tsiu C. Chan , Frank R. Bryant , John L. Walters
发明人： Tsiu C. Chan , Frank R. Bryant , John L. Walters
IPC分类号： H01L21/768 , H01L23/532 , H01L27/11 , H01L29/76 , H01L29/94
CPC分类号： H01L27/1104 , H01L21/76895 , H01L23/53271 , H01L2924/0002 , Y10S257/903
摘要： An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.
摘要翻译：互连结构及其形成方法适用于诸如SRAM器件的集成电路。该结构使用多晶硅互连电平的掩模将P-N结移动到多晶硅互连线内的区域，而不是在衬底处。然后可以使用形成在多晶硅互连结构上的难熔金属硅化物来短路该P-N结。

5. 发明授权

US5196909A Capacitor for DRAM cell 失效
标题翻译： DRAM单元电容器
公开(公告)号：US5196909A
公开(公告)日：1993-03-23
申请号：US697227
申请日：1991-05-07
申请人： Tsiu C. Chan , Frank R. Bryant
发明人： Tsiu C. Chan , Frank R. Bryant
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10817 , H01L28/40
摘要： A capacitor suitable for use with a DRAM memory cell is composed of multiple layers of polycrystalline silicon. The storage node is formed from a polycrystalline silicon layer sandwiched between two polysilicon ground plate layers. Such a structure nearly doubles the capacitance for a given chip surface area used. First the bottom polycrystalline silicon plate layer is fabricated, followed by an isolation step and fabrication of the storage node polycrystalline silicon layer. Following another isolation step, the polycrystalline silicon top plate layer is then formed and connected to the bottom plate layer.
摘要翻译：适用于DRAM存储单元的电容器由多层多晶硅组成。存储节点由夹在两个多晶硅接地板层之间的多晶硅层形成。这种结构对于所使用的给定芯片表面积几乎使电容增加一倍。首先制造底部多晶硅板层，然后进行隔离步骤和存储节点多晶硅层的制造。在另一隔离步骤之后，然后形成多晶硅顶板层并将其连接到底板层。

6. 发明授权

US5702979A Method of forming a landing pad structure in an integrated circuit 失效
标题翻译：在集成电路中形成着陆焊盘结构的方法
公开(公告)号：US5702979A
公开(公告)日：1997-12-30
申请号：US361760
申请日：1994-12-22
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/02 , H01L21/44
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductrive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.
摘要翻译：提供一种用于形成半导体集成电路的改进的着陆焊盘的方法，以及根据该集成电路形成的集成电路。通过第一介电层形成第一开口以暴露扩散区域的一部分。在第一介电层上和开口中形成第一多晶硅着陆焊盘。该着陆垫将提供更小的几何形状，并满足严格的设计规则，例如接触空间到门。在有源区上方的多晶硅着陆垫上形成电介质袋。在多晶硅着陆焊盘和电介质槽上方形成第二导电焊盘。第二电介质层形成在着陆焊盘上，具有通过其暴露出一部分着陆焊盘的第二开口。在第二接触开口中形成诸如铝的导电接触。导电触点将通过着陆焊盘与扩散区域电连接。可以容忍在着陆垫上的导电触头开口的不对准，而不会侵入设计规则。着陆垫和电介质袋将增强平面化，以提供第二开口中的金属接触件的更好的台阶覆盖。

7. 发明授权

US5448091A Method of making contact alignment for nonvolatile memory devices 失效
标题翻译：非易失性存储器件接触对准方法
公开(公告)号：US5448091A
公开(公告)日：1995-09-05
申请号：US307475
申请日：1994-09-16
申请人： Frank R. Bryant , Tsiu C. Chan
发明人： Frank R. Bryant , Tsiu C. Chan
IPC分类号： G11C17/00 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/68
CPC分类号： H01L21/76802 , H01L27/115 , Y10S257/90
摘要： A layout and fabrication technique for EPROMs and similar devices includes a preferred technique for partially self-aligning bit line contacts. In addition, a self-aligned, buried Vss line is provided which is in contact with the substrate for its entire length. This provides a highly conductive Vss line, allowing the size of such line to be diminished. The use of a buried Vss contact line and a partially self-aligned bit line contact contributes to a device layout having minimum cell sizes for a given feature size.
摘要翻译： EPROM和类似器件的布局和制造技术包括用于部分自对准位线触点的优选技术。另外，提供了自对准埋置的Vss线，其与衬底的整个长度接触。这提供了高导电性Vss线，允许这种线的尺寸减小。使用埋入的Vss接触线和部分自对准位线接触有助于针对给定特征尺寸具有最小单元尺寸的器件布局。

8. 发明授权

US5426065A Method of making transistor devices in an SRAM cell 失效
标题翻译：在SRAM单元中制造晶体管器件的方法
公开(公告)号：US5426065A
公开(公告)日：1995-06-20
申请号：US159462
申请日：1993-11-30
申请人： Tsiu C. Chan , Frank R. Bryant
发明人： Tsiu C. Chan , Frank R. Bryant
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/10 , H01L27/11 , H01L29/78 , H01L21/8229
CPC分类号： H01L27/11 , Y10S148/163
摘要： An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node. The first and second transfer gate transistors each include a gate oxide layer having a first thickness, and the first and second pull-down transistors each include a gate oxide layer having a second thickness, wherein and the first thickness is different from the second thickness.
摘要翻译：一种具有第一和第二传输门晶体管的SRAM存储单元。第一传输门晶体管包括连接到位线的第一源极/漏极，第二传输门晶体管具有连接到补码位线的第一源极/漏极。每个传输门晶体管具有连接到字线的栅极。 SRAM存储单元还包括被配置为存储锁存器的第一和第二下拉晶体管。第一下拉晶体管具有连接到所述第一传输栅极晶体管的第二源极/漏极的第一源极/漏极; 所述第二下拉晶体管具有连接到所述第二传输栅极晶体管的第二源极/漏极的第一源极/漏极。第一和第二下拉晶体管都具有连接到电源电压节点的第二源极/漏极。第一和第二传输门晶体管各自包括具有第一厚度的栅极氧化物层，并且第一和第二下拉晶体管各自包括具有第二厚度的栅极氧化物层，其中第一厚度不同于第二厚度。

9. 发明授权

US5376571A Method of making contact alignment for nonvolatile memory devices 失效
标题翻译：非易失性存储器件接触对准方法
公开(公告)号：US5376571A
公开(公告)日：1994-12-27
申请号：US118843
申请日：1993-09-10
申请人： Frank R. Bryant , Tsiu C. Chan
发明人： Frank R. Bryant , Tsiu C. Chan
IPC分类号： G11C17/00 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/441
CPC分类号： H01L21/76802 , H01L27/115 , Y10S257/90
摘要： A layout and fabrication technique for EPROMs and similar devices includes a preferred technique for partially self-aligning bit line contacts. In addition, a self-aligned, buried Vss line is provided which is in contact with the substrate for its entire length. This provides a highly conductive Vss line, allowing the size of such line to be diminished. The use of a buried Vss contact line and a partially self-aligned bit line contact contributes to a device layout having minimum cell sizes for a given feature size.
摘要翻译： EPROM和类似器件的布局和制造技术包括用于部分自对准位线触点的优选技术。另外，提供了自对准埋置的Vss线，其与衬底的整个长度接触。这提供了高导电性Vss线，允许这种线的尺寸减小。使用埋入的Vss接触线和部分自对准位线接触有助于针对给定特征尺寸具有最小单元尺寸的器件布局。

10. 发明授权

US5310692A Method of forming a MOSFET structure with planar surface 失效
标题翻译：形成具有平面表面的MOSFET结构的方法
公开(公告)号：US5310692A
公开(公告)日：1994-05-10
申请号：US889822
申请日：1992-05-29
申请人： Tsiu C. Chan , Frank R. Bryant
发明人： Tsiu C. Chan , Frank R. Bryant
IPC分类号： H01L21/76 , H01L21/28 , H01L21/3105 , H01L21/32 , H01L21/762 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/265
CPC分类号： H01L29/4933 , H01L21/28123 , H01L21/31055 , H01L21/32 , H01L21/76202 , H01L29/42376 , H01L2924/0002
摘要： A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photoresist layer is then formed and patterned over the silicon nitride layer. The silicon nitride layer and the conductive layer are etched to form an opening exposing a portion of the substrate. The photoresist layer is then removed. The exposed substrate and a portion of the conductive layer exposed along the sidewalls in the opening are oxidized. An planarizing insulating layer such as spin-on-glass is formed over the silicon nitride layer and in the opening. The insulating layer is etched back to expose the silicon nitride wherein an upper surface of the insulating layer is level with an upper surface of the conductive layer. The silicon nitride layer is then removed. A planar silicide layer is then formed over the conductive layer.
摘要翻译：提供了一种用于半导体集成电路的平面的方法和根据该集成电路形成的集成电路。在衬底上形成导电层。在导电层上形成氮化硅层。然后在氮化硅层上形成并图案化光致抗蚀剂层。蚀刻氮化硅层和导电层以形成露出衬底的一部分的开口。然后除去光致抗蚀剂层。暴露的基板和沿开口侧壁暴露的导电层的一部分被氧化。在氮化硅层和开口中形成平面化绝缘层，例如旋涂玻璃。将绝缘层回蚀刻以露出氮化硅，其中绝缘层的上表面与导电层的上表面平齐。然后去除氮化硅层。然后在导电层上形成平面硅化物层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式