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1. 发明授权

US07737748B2 Level shifter of semiconductor device and method for controlling duty ratio in the device 有权
标题翻译：半导体器件的电平移位器和装置中占空比的控制方法
公开(公告)号：US07737748B2
公开(公告)日：2010-06-15
申请号：US11986841
申请日：2007-11-27
申请人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
发明人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
IPC分类号： H03K3/017
CPC分类号： H03K3/35613 , H03K3/017
摘要： A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.
摘要翻译：提供半导体器件的电平移位器和控制占空比的方法。电平移位器包括具有施加电源电压的源的第一和第二PMOS晶体管，具有施加接地电压的源的第一和第二NMOS晶体管，具有连接到第一和第二漏极的漏极的源的第三和第四NMOS晶体管施加电源电压的NMOS晶体管和栅极; 以及电压控制延迟单元，用于接收施加到第一NMOS晶体管的栅极的输入信号，反相输入信号的电平，确定反相输入信号的电压是否应当响应于电压控制信号而被充电，输出控制延迟时间的反相输入信号的电压，并将反相输入信号施加到第二NMOS晶体管的栅极。

2. 发明申请

US20080186075A1 Level shifter of semiconductor device and method for controlling duty ratio in the device 有权
标题翻译：半导体器件的电平移位器和装置中占空比的控制方法
公开(公告)号：US20080186075A1
公开(公告)日：2008-08-07
申请号：US11986841
申请日：2007-11-27
申请人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
发明人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
IPC分类号： H03L5/00
CPC分类号： H03K3/35613 , H03K3/017
摘要： A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.
摘要翻译：提供半导体器件的电平移位器和控制占空比的方法。电平移位器包括具有施加电源电压的源的第一和第二PMOS晶体管，具有施加接地电压的源的第一和第二NMOS晶体管，具有连接到第一和第二漏极的漏极的源的第三和第四NMOS晶体管施加电源电压的NMOS晶体管和栅极; 以及电压控制延迟单元，用于接收施加到第一NMOS晶体管的栅极的输入信号，反相输入信号的电平，确定反相输入信号的电压是否应当响应于电压控制信号而被充电，输出控制延迟时间的反相输入信号的电压，并将反相输入信号施加到第二NMOS晶体管的栅极。

3. 发明授权

US06812765B2 Pulsed signal transition delay adjusting circuit 失效
标题翻译：脉冲信号转换延时调整电路
公开(公告)号：US06812765B2
公开(公告)日：2004-11-02
申请号：US10425077
申请日：2003-04-28
申请人： Kyu-hyoun Kim , Dae-Hyun Chung
发明人： Kyu-hyoun Kim , Dae-Hyun Chung
IPC分类号： H03H1126
CPC分类号： H03K5/08 , H03H11/265 , H03K5/13 , H03K2005/00071
摘要： A delay circuit has an input node receives an input pulsed signal. A buffer transfers the input signal to a floating node. A detector outputs to an output node an output voltage that has a first level, if the voltage at the floating node is below a threshold, and a second level otherwise. Two similar branches are used, one for controlling delays in the rising transitions and one for controlling delays in the falling transitions. For each branch, a reference terminal carries a reference voltage for biasing the floating node. A capacitor and a switch are coupled between the reference terminal and the floating node. The switch opens and closes responsive to the output voltage. When it opens, it shorts out the capacitor. An optional phase detector and delay code generator may be in a feedback arrangement, for continuously adjusting the reference voltages.
摘要翻译：延迟电路具有输入节点接收输入脉冲信号。缓冲器将输入信号传送到浮动节点。如果浮动节点处的电压低于阈值，则检测器向输出节点输出具有第一电平的输出电压，否则输出第二电平。使用两个相似的分支，一个用于控制上升转换中的延迟，一个用于控制下降转换中的延迟。对于每个分支，参考端子携带用于偏置浮动节点的参考电压。电容器和开关耦合在参考端和浮动节点之间。开关响应输出电压打开和关闭。当它打开时，它会使电容器短路。可选的相位检测器和延迟码发生器可以是反馈装置，用于连续地调节参考电压。

4. 发明授权

US06778464B2 Expanded operating frequency synchronous semiconductor memory device having wave pipeline structure and wave pipeline control method thereof 有权
标题翻译：具有波浪管线结构和波浪管线控制方法的扩展工作频率同步半导体存储器件
公开(公告)号：US06778464B2
公开(公告)日：2004-08-17
申请号：US10288830
申请日：2002-11-06
申请人： Dae-hyun Chung
发明人： Dae-hyun Chung
IPC分类号： G11C800
CPC分类号： G11C7/1093 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1087
摘要： Synchronous semiconductor memory devices and methods of operating are provided. The device has a latency N and includes a memory cell array, a stack unit having N storage units and a frequency detector that provides an output signal based on the relationship of the frequency of operation clock to a predetermined frequency. A control circuit controls the stack unit in response to the output signal of the frequency detector. The control circuit latches data read from the memory and controls the stack unit so that the latched data is stored from a clock cycle when a read command is sent until an N-th cycle afterwards if the clock frequency is greater than the predetermined frequency and delays the latched data for one cycle and controls the stack unit so that the delayed data is stored from one cycle after the read command is sent until an N+1 cycle afterwards.
摘要翻译：提供了同步半导体存储器件和操作方法。该设备具有延迟N，并且包括存储单元阵列，具有N个存储单元的堆叠单元和基于操作时钟频率与预定频率的关系提供输出信号的频率检测器。控制电路根据频率检测器的输出信号控制堆栈单元。控制电路锁存从存储器读取的数据并控制堆栈单元，使得当读命令被发送到第N个周期之后，如果时钟频率大于预定频率并且延迟，则从锁存数据存储从时钟周期一个周期的锁存数据并控制堆栈单元，以便在发送读命令之后从一个周期开始存储延迟的数据，直到N + 1个周期后。

5. 发明申请

US20090174445A1 Semiconductor devices, methods of operating semiconductor devices, and systems having the same 有权
标题翻译：半导体器件，半导体器件的操作方法以及具有该半导体器件的系统
公开(公告)号：US20090174445A1
公开(公告)日：2009-07-09
申请号：US12318773
申请日：2009-01-08
申请人： Jin Gook Kim , Dae Hyun Chung , Seung Jun Bae , Seung Hoon Lee , Won Hwa Shin
发明人： Jin Gook Kim , Dae Hyun Chung , Seung Jun Bae , Seung Hoon Lee , Won Hwa Shin
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C2207/107 , H04L7/0008 , H04L7/0091
摘要： A semiconductor device includes a selection circuit and a phase detector. The selection circuit, in response to a first selection signal output from a controller, outputs as a timing signal a first clock signal output from the controller or an output signal of a PLL using the first clock signal as a first input. The phase detector generates a voltage signal indicating a phase difference between a second clock signal output from the controller and the timing signal output from the selection circuit. The semiconductor device further includes a data port, a memory core storing data, and a serializer, in response to the timing signal output from the selection circuit, serializing the data output from the memory core and outputting serialized data to the controller via the data port. The first selection signal is generated by the controller based on at least one of the voltage signal and the data output to the controller via the data port.
摘要翻译：半导体器件包括选择电路和相位检测器。选择电路响应于从控制器输出的第一选择信号，作为定时信号输出从控制器输出的第一时钟信号或使用第一时钟信号作为第一输入的PLL的输出信号。相位检测器产生指示从控制器输出的第二时钟信号与从选择电路输出的定时信号之间的相位差的电压信号。半导体器件还包括响应于从选择电路输出的定时信号的数据端口，存储数据的存储器核心和串行器，串行化从存储器核心输出的数据，并经由数据端口将串行数据输出到控制器。第一选择信号由控制器基于电压信号和通过数据端口输出到控制器的数据中的至少一个来产生。

6. 发明申请

US20080169536A1 Semiconductor device and signal terminating method thereof 失效
标题翻译：半导体装置及其信号终端方法
公开(公告)号：US20080169536A1
公开(公告)日：2008-07-17
申请号：US12007322
申请日：2008-01-09
申请人： Dae-Hyun Chung
发明人： Dae-Hyun Chung
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L23/66 , H01L23/64 , H01L2924/0002 , H01L2924/19051 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device may include a semiconductor chip including a signal terminating resistor coupled between a signal input pad and a first ground voltage pad, a semiconductor package including a signal input terminal and a first ground voltage terminal, the signal input terminal being electrically coupled to the signal input pad of the semiconductor chip and the first ground voltage terminal being electrically coupled to the first ground voltage pad of the semiconductor chip, a capacitor and a resistor that are coupled between the signal input terminal and the first ground voltage terminal, and a first inductor realized by coupling the signal input terminal and the signal input pad.
摘要翻译：半导体器件可以包括半导体芯片，其包括耦合在信号输入焊盘和第一接地电压焊盘之间的信号终端电阻器，包括信号输入端子和第一接地电压端子的半导体封装件，所述信号输入端子电耦合到半导体芯片的信号输入焊盘和第一接地电压端子电耦合到半导体芯片的第一接地电压焊盘，耦合在信号输入端子和第一接地电压端子之间的电容器和电阻器，以及第一电感通过耦合信号输入端和信号输入板实现。

7. 发明授权

US06882580B2 Memory devices having power supply routing for delay locked loops that counteracts power noise effects 有权
标题翻译：具有用于抵消功率噪声影响的延迟锁定环路的电源路由的存储器件
公开(公告)号：US06882580B2
公开(公告)日：2005-04-19
申请号：US10358739
申请日：2003-02-05
申请人： Hyun-wook Lim , Dae-hyun Chung
发明人： Hyun-wook Lim , Dae-hyun Chung
IPC分类号： G11C7/22 , G11C8/00 , G11C11/401 , G11C11/407 , G11C11/4074 , G11C11/4076 , H03K5/13 , H03L7/00 , G11C7/00
CPC分类号： G11C7/222 , G11C7/22 , G11C2207/105
摘要： A memory device includes first and second power supply pads configured to be connected to a power supply. The memory device further includes a data output circuit that receives power via the first power supply pad and outputs data responsive to an internal clock signal, and a delay-locked loop (DLL) circuit that receives power via the second power supply pad independently of the first power supply pad and that generates the internal clock signal responsive to an external clock signal.
摘要翻译：存储器件包括被配置为连接到电源的第一和第二电源焊盘。存储器件还包括数据输出电路，其经由第一电源焊盘接收电力并响应于内部时钟信号输出数据;以及延迟锁定环路（DLL）电路，其经由第二电源焊盘独立地接收电力，第一电源焊盘，并且响应于外部时钟信号产生内部时钟信号。

8. 发明授权

US06327217B1 Variable latency buffer circuits, latency determination circuits and methods of operation thereof 失效
标题翻译：可变延迟缓冲电路，等待时间确定电路及其操作方法
公开(公告)号：US06327217B1
公开(公告)日：2001-12-04
申请号：US09679784
申请日：2000-10-05
申请人： Dae-hyun Chung
发明人： Dae-hyun Chung
IPC分类号： G11C800
CPC分类号： G11C7/222 , G01R31/30 , G11C7/1072 , G11C7/22
摘要： A variable delay buffer circuit, as might be used in a synchronous DRAM, includes a buffer circuit that receives an input signal and generates an output signal therefrom responsive to an output enable signal. An output enable signal generation circuit receives a latency indicating signal and generates the output enable signal responsive to a command signal with a delay that is based on the latency indicating signal. A latency interval definition circuit receives a clock signal and generates at least one latency interval defining signal that defines at least one latency interval. A latency indication circuit receives the at least one latency interval defining signal and a test signal that is delayed a predetermined delay with respect to the clock signal and generates the latency indicating signal therefrom. Related methods are also discussed.
摘要翻译：可以在同步DRAM中使用的可变延迟缓冲器电路包括缓冲电路，其接收输入信号并根据输出使能信号产生输出信号。输出使能信号发生电路接收等待时间指示信号，并响应于基于等待时间指示信号的延迟的命令信号产生输出使能信号。延迟间隔定义电路接收时钟信号并产生定义至少一个等待时间间隔的至少一个等待时间间隔定义信号。延迟指示电路接收至少一个等待时间间隔定义信号和相对于时钟信号延迟预定延迟的测试信号，并从其生成等待时间指示信号。还讨论了相关方法。

9. 发明授权

US07038971B2 Multi-clock domain data input-processing device having clock-receiving locked loop and clock signal input method thereof 失效
标题翻译：具有时钟接收锁定环的多时钟域数据输入处理装置及其时钟信号输入方法
公开(公告)号：US07038971B2
公开(公告)日：2006-05-02
申请号：US10288540
申请日：2002-11-06
申请人： Dae-Hyun Chung
发明人： Dae-Hyun Chung
IPC分类号： G11C8/00
CPC分类号： G06F5/06 , G11C7/1072 , G11C7/222 , H03L7/0814 , H04L7/0008 , H04L7/0037 , H04L7/0045 , H04L7/02
摘要： A multi-clock-domain data input processing device preferably includes: a clock-signal-receiving synchronous circuit that generates an output clocking signal by phase-delaying a first clock signal; a data input part having a delay locked loop (DLL); and an input-processing part. The data input part preferably inputs data in response to the first clock signal and the input-processing part transfers data in response to a second clock signal having a timing different from that of the first clock signal. A clock-signal applying method for operating the multi-clock-domain data input-processing device preferably includes the steps of: applying a plurality of clock signals to a signal-receiving clock conversion part; and applying a delayed clocking signal outputted from the DLL to the remaining parts of the data input-processing device.
摘要翻译：多时钟域数据输入处理装置优选地包括：时钟信号接收同步电路，通过相位延迟第一时钟信号来产生输出时钟信号; 具有延迟锁定环（DLL）的数据输入部分; 和输入处理部。数据输入部分优选地响应于第一时钟信号输入数据，并且输入处理部分响应于具有与第一时钟信号的定时不同的定时的第二时钟信号来传送数据。用于操作多时钟域数据输入处理装置的时钟信号施加方法优选地包括以下步骤：将多个时钟信号施加到信号接收时钟转换部分; 以及将从DLL输出的延迟时钟信号应用于数据输入处理装置的其余部分。

10. 发明授权

US08306169B2 Semiconductor devices, methods of operating semiconductor devices, and systems having the same 有权
标题翻译：半导体器件，半导体器件的操作方法以及具有该半导体器件的系统
公开(公告)号：US08306169B2
公开(公告)日：2012-11-06
申请号：US12318773
申请日：2009-01-08
申请人： Jin Gook Kim , Dae Hyun Chung , Seung Jun Bae , Seung Hoon Lee , Won Hwa Shin
发明人： Jin Gook Kim , Dae Hyun Chung , Seung Jun Bae , Seung Hoon Lee , Won Hwa Shin
IPC分类号： H04L12/66
CPC分类号： H03L7/0812 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C2207/107 , H04L7/0008 , H04L7/0091
摘要： A semiconductor device includes a selection circuit and a phase detector. The selection circuit, in response to a first selection signal output from a controller, outputs as a timing signal a first clock signal output from the controller or an output signal of a PLL using the first clock signal as a first input. The phase detector generates a voltage signal indicating a phase difference between a second clock signal output from the controller and the timing signal output from the selection circuit. The semiconductor device further includes a data port, a memory core storing data, and a serializer, in response to the timing signal output from the selection circuit, serializing the data output from the memory core and outputting serialized data to the controller via the data port. The first selection signal is generated by the controller based on at least one of the voltage signal and the data output to the controller via the data port.
摘要翻译：半导体器件包括选择电路和相位检测器。选择电路响应于从控制器输出的第一选择信号，作为定时信号输出从控制器输出的第一时钟信号或使用第一时钟信号作为第一输入的PLL的输出信号。相位检测器产生指示从控制器输出的第二时钟信号与从选择电路输出的定时信号之间的相位差的电压信号。半导体器件还包括响应于从选择电路输出的定时信号的数据端口，存储数据的存储器核心和串行器，串行化从存储器核心输出的数据，并经由数据端口将串行数据输出到控制器。第一选择信号由控制器基于电压信号和通过数据端口输出到控制器的数据中的至少一个来产生。

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