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1. 发明授权

US07213220B2 Method for verification of gate level netlists using colored bits 失效
标题翻译：使用彩色位验证门级网表的方法
公开(公告)号：US07213220B2
公开(公告)日：2007-05-01
申请号：US11009350
申请日：2004-12-10
申请人： Bodo Hoppe , Christoph Jaeschke , Johannes Koesters
发明人： Bodo Hoppe , Christoph Jaeschke , Johannes Koesters
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention relates to the field of computer hardware locic circuits, and in particular to a method for verifying the proper operation of a digital logic circuit, and in particular to symbolic simulation of a gate-level netlist corresponding to said hardware logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) analyzing symbolic expressions visible at predetermined locations within said logic; b) determining, which nets in the netlist carry complex symbolic expressions, which comprise more than one symbol; c) replacing said complex expressions with a “crunshed color”, for cutting off said complex symbolic expression from further propagation through the netlist; d) continuing said symbolic simulation including said crunched color information on predetermined nets.
摘要翻译：本发明涉及计算机硬件定位电路领域，特别涉及用于验证数字逻辑电路的正确操作的方法，特别涉及对应于所述硬件逻辑电路的门级网表的符号仿真。为了在功能，详尽的仿真和符号仿真领域增加一个有用的替代方案，提出了执行以下步骤：a）分析在所述逻辑内的预定位置可见的符号表达式; b）确定网表中的网络携带多于一个符号的复杂符号表达式; c）用“重要颜色”代替所述复合表达式，以便将所述复杂符号表达式从进一步传播通过网表切断; d）继续所述符号模拟，其包括在预定网上的所述嘎吱嘎吱的颜色信息。

2. 发明授权

US07565636B2 System for performing verification of logic circuits 失效
标题翻译：用于执行逻辑电路验证的系统
公开(公告)号：US07565636B2
公开(公告)日：2009-07-21
申请号：US12060953
申请日：2008-04-02
申请人： Bodo Hoppe , Christoph Jaeschke , Johannes Koesters
发明人： Bodo Hoppe , Christoph Jaeschke , Johannes Koesters
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention relates to a system for verifying the proper operation of a digital logic circuit and program product therefore. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) marking a net with an additional property other than a bit value, wherein both said bit value and said additional property are valid at said net at a given time; b) propagating the marking of the net according to a set of predetermined semantic rules, wherein the set of predetermined semantic rules are defined according to a predetermined simulation; and c) generating an output at a predetermined downstream location of the digital logic circuit, said output providing an information, if or if not said property has propagated through the circuit to said predetermined downstream location or not.
摘要翻译：本发明涉及一种用于验证数字逻辑电路和程序产品的正确操作的系统。为了在功能，详尽的仿真和符号仿真领域添加有用的替代方案，提出了执行以下步骤：a）用除位值之外的附加属性标记网，其中所述位值和所述额外财产在特定时间在所述净值有效; b）根据一组预定的语义规则传播网络的标记，其中根据预定的模拟定义所述一组预定语义规则; 以及c）在所述数字逻辑电路的预定下游位置处产生输出，所述输出提供信息，如果或者不是所述属性已经通过所述电路传播到所述预定下游位置。

3. 发明申请

US20090132983A1 Driving Values to DC Adjusted/Untimed Nets to Identify Timing Problems 有权
标题翻译：向直流调整/未绑定网络驱动价值，以确定时序问题
公开(公告)号：US20090132983A1
公开(公告)日：2009-05-21
申请号：US12271588
申请日：2008-11-14
申请人： Robert B. Gass , Yee Ja , Christoph Jaeschke
发明人： Robert B. Gass , Yee Ja , Christoph Jaeschke
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An apparatus and computer program product for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The apparatus and computer program product may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the apparatus and computer program product, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the apparatus and computer program product may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.
摘要翻译：提供了一种用于驱动集成电路设计的“无关心”（DC）调整/未定型网络的值的装置和计算机程序产品，从而识别定时问题。该装置和计算机程序产品可以用于例如集成电路的逻辑内置自检（LBIST）测试，其中用于集成电路的正常功能模式的DC调节（dcadj）网络可能不被直流调整用于LBIST模式。通过使用设备和计算机程序产品，可以通过使用模拟或半正式/形式分析，使与DC调整/未定义网相关的定时相关问题变得明显。例如，关于DC调整/未定义的网络，设备和计算机程序产品可以识别关于维持其DC调整值的任何这些网络的违规。可以在不干扰定时网络的静态时序分析的情况下进行对DC调整/未定义网的违规的识别。

4. 发明授权

US07490305B2 Method for driving values to DC adjusted/untimed nets to identify timing problems 失效
标题翻译：将值驱动到DC调整/未定义网络以识别时序问题的方法
公开(公告)号：US07490305B2
公开(公告)日：2009-02-10
申请号：US11457865
申请日：2006-07-17
申请人： Robert B. Gass , Yee Ja , Christoph Jaeschke
发明人： Robert B. Gass , Yee Ja , Christoph Jaeschke
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The system and method may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the system and method, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the system and method may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.
摘要翻译：提供了一种用于驱动集成电路设计的“不关心”（DC）调整/未定网的值从而识别定时问题的方法。该系统和方法可以用于例如集成电路的逻辑内置自检（LBIST）测试，其中用于集成电路的正常功能模式的DC调节（dcadj）网络可以不被LB调整为LBIST 模式。通过使用系统和方法，通过使用模拟或半正规/形式分析，可以使与DC调整/未定义网相关的定时相关问题变得明显。例如，关于DC调整/未定义的网络，系统和方法可以识别关于维持其DC调整值的任何这些网络的违规。可以在不干扰定时网络的静态时序分析的情况下进行对DC调整/未定义网的违规的识别。

5. 发明申请

US20080276140A1 SEMICONDUCTOR CHIP WITH A PLURALITY OF SCANNABLE STORAGE ELEMENTS AND A METHOD FOR SCANNING STORAGE ELEMENTS ON A SEMICONDUCTOR CHIP 有权
标题翻译：具有多重可扫描存储元件的半导体芯片和用于扫描半导体芯片上的存储元件的方法
公开(公告)号：US20080276140A1
公开(公告)日：2008-11-06
申请号：US12042944
申请日：2008-03-05
申请人： Tobias Gemmeke , Christoph Jaeschke , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Jochen Preiss
发明人： Tobias Gemmeke , Christoph Jaeschke , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Jochen Preiss
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318575
摘要： A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.
摘要翻译：分为功率域的半导体芯片，至少一个功率域被单独激活或去激活，并且可扫描存储元件的至少一部分互连到一个或多个扫描链。至少一个扫描链被连续地分成扫描链部分，并且扫描链部分被布置在一个功率域内。对于至少一个扫描链部分，提供旁路线以通过扫描数据，并且提供至少一个选择单元用于根据相应功率域的激活或去激活状态在旁路线和对应的扫描链部分之间进行选择。

6. 发明申请

US20120151423A1 LARGE SCALE FORMAL ANALYSIS BY STRUCTURAL PREPROCESSING 审中-公开
标题翻译：通过结构预处理的大规模形式分析
公开(公告)号：US20120151423A1
公开(公告)日：2012-06-14
申请号：US13284489
申请日：2011-10-28
申请人： Jason R. Baumgartner , Tilman Gloekler , Christoph Jaeschke , Ralf Ludewig
发明人： Jason R. Baumgartner , Tilman Gloekler , Christoph Jaeschke , Ralf Ludewig
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： An improved method for performing a formal verification of a property in an electronic circuit design comprises: specifying at least one safety property in the electronic circuit design at a register-transfer level, setting boundaries of a logic cone to a start level according to a configurable structural design criterion, extracting the logic cone from the electronic circuit design based on the at least one specified safety property and the set boundaries, executing a formal verification tool on the logic cone to verify the at least one specified property, extending the boundary of the logic cone according to a configurable structural design criterion and performing the extracting and executing on the new logic cone, if the verification result does not satisfy the at least one safety property.
摘要翻译：一种用于执行电子电路设计中的属性的形式验证的改进方法包括：在寄存器传送级别指定电子电路设计中的至少一个安全属性，根据可配置的方式将逻辑锥的边界设置为起始级别结构设计标准，基于至少一个指定的安全属性和设定的边界，从电子电路设计中提取逻辑锥，在逻辑锥上执行形式验证工具，以验证至少一个指定的属性，根据可配置结构设计标准的逻辑锥，并且如果验证结果不满足至少一个安全属性，则执行在新的逻辑锥上的提取和执行。

7. 发明授权

US07886244B2 Driving values to DC adjusted/untimed nets to identify timing problems 有权
标题翻译：将值驱动到DC调整/未定义的网络以识别时序问题
公开(公告)号：US07886244B2
公开(公告)日：2011-02-08
申请号：US12271588
申请日：2008-11-14
申请人： Robert B. Gass , Yee Ja , Christoph Jaeschke
发明人： Robert B. Gass , Yee Ja , Christoph Jaeschke
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031
摘要： An apparatus and computer program product for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The apparatus and computer program product may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the apparatus and computer program product, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the apparatus and computer program product may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.
摘要翻译：提供了一种用于驱动集成电路设计的“无关心”（DC）调整/未定型网络的值的装置和计算机程序产品，从而识别定时问题。该装置和计算机程序产品可以用于例如集成电路的逻辑内置自检（LBIST）测试，其中用于集成电路的正常功能模式的DC调节（dcadj）网络可能不被直流调整用于LBIST模式。通过使用设备和计算机程序产品，可以通过使用模拟或半正式/形式分析，使与DC调整/未定义网相关的定时相关问题变得明显。例如，关于DC调整/未定义的网络，设备和计算机程序产品可以识别关于维持其DC调整值的任何这些网络的违规。可以在不干扰定时网络的静态时序分析的情况下进行对DC调整/未定义网的违规的识别。

8. 发明申请

US20080016480A1 System and Method for Driving Values to DC Adjusted/Untimed Nets to Identify Timing Problems 失效
标题翻译：用于向直流调整/无源网络驱动价值以识别时序问题的系统和方法
公开(公告)号：US20080016480A1
公开(公告)日：2008-01-17
申请号：US11457865
申请日：2006-07-17
申请人： Robert B. Gass , Yee Ja , Christoph Jaeschke
发明人： Robert B. Gass , Yee Ja , Christoph Jaeschke
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The system and method may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the system and method, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the system and method may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.
摘要翻译：提供了一种用于驱动集成电路设计的“无关心”（DC）调整/未定型网络的值以便识别定时问题的系统和方法。该系统和方法可以用于例如集成电路的逻辑内置自检（LBIST）测试，其中用于集成电路的正常功能模式的DC调节（dcadj）网络可以不被LB调整为LBIST 模式。通过使用系统和方法，通过使用模拟或半正规/形式分析，可以使与DC调整/未定义网相关的定时相关问题变得明显。例如，关于DC调整/未定义的网络，系统和方法可以识别关于维持其DC调整值的任何这些网络的违规。可以在不干扰定时网络的静态时序分析的情况下进行对DC调整/未定义网的违规的识别。

9. 发明授权

US07996738B2 Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip 有权
标题翻译：具有多个可扫描存储元件的半导体芯片和用于扫描半导体芯片上的存储元件的方法
公开(公告)号：US07996738B2
公开(公告)日：2011-08-09
申请号：US12042944
申请日：2008-03-05
申请人： Tobias Gemmeke , Christoph Jaeschke , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Jochen Preiss
发明人： Tobias Gemmeke , Christoph Jaeschke , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Jochen Preiss
IPC分类号： G01R31/28
CPC分类号： G01R31/318575
摘要： A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.
摘要翻译：分为功率域的半导体芯片，至少一个功率域被单独激活或去激活，并且可扫描存储元件的至少一部分互连到一个或多个扫描链。至少一个扫描链被连续地分成扫描链部分，并且扫描链部分被布置在一个功率域内。对于至少一个扫描链部分，提供旁路线以通过扫描数据，并且提供至少一个选择单元用于根据相应功率域的激活或去激活状态在旁路线和对应的扫描链部分之间进行选择。

10. 发明申请

US20090228751A1 METHOD FOR PERFORMING LOGIC BUILT-IN-SELF-TEST CYCLES ON A SEMICONDUCTOR CHIP AND A CORRESPONDING SEMICONDUCTOR CHIP WITH A TEST ENGINE 审中-公开
标题翻译：用于在半导体芯片上执行逻辑内置自测试循环的方法和与测试引擎相关的半导体芯片
公开(公告)号：US20090228751A1
公开(公告)日：2009-09-10
申请号：US12125476
申请日：2008-05-22
申请人： Tilman Gloekler , Christoph Jaeschke , Thuyen Le , Martin Padeffke
发明人： Tilman Gloekler , Christoph Jaeschke , Thuyen Le , Martin Padeffke
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318536 , G01R31/318547
摘要： A method, structure and design system for performing logic built-in-self-test (LBIST) cycles on a semiconductor chip with a plurality of logic circuits and a plurality of storage elements connected serially to a number of LBIST stumps (pattern segments) between a pseudo-random-pattern generator (30) and a multiple-input-signature register. The semiconductor chip is subdivided into partitions, such that LBIST cycles may be run separately or in parallel for one or more partitions. The LBIST cycles may also be run separately or in parallel inter-connections between the partitions. The partitions to be tested are controlled by at least one corresponding clock signal, and the inter-connections to be tested are controlled by at least one corresponding clock signal.
摘要翻译：一种用于在半导体芯片上执行逻辑内置自检（LBIST）周期的方法，结构和设计系统，其具有多个逻辑电路和多个存储元件，所述多个逻辑电路和多个存储元件串联连接到多个LBIST树桩（图案段）之间，伪随机模式生成器（30）和多输入签名寄存器。半导体芯片被细分为分区，使得LBIST周期可以针对一个或多个分区单独运行或并行运行。 LBIST循环也可以分开运行或在分区之间并行连接。要测试的分区由至少一个对应的时钟信号控制，并且待测试的互连由至少一个相应的时钟信号控制。

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