专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120151423A1 LARGE SCALE FORMAL ANALYSIS BY STRUCTURAL PREPROCESSING 审中-公开
标题翻译：通过结构预处理的大规模形式分析
公开(公告)号：US20120151423A1
公开(公告)日：2012-06-14
申请号：US13284489
申请日：2011-10-28
申请人： Jason R. Baumgartner , Tilman Gloekler , Christoph Jaeschke , Ralf Ludewig
发明人： Jason R. Baumgartner , Tilman Gloekler , Christoph Jaeschke , Ralf Ludewig
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： An improved method for performing a formal verification of a property in an electronic circuit design comprises: specifying at least one safety property in the electronic circuit design at a register-transfer level, setting boundaries of a logic cone to a start level according to a configurable structural design criterion, extracting the logic cone from the electronic circuit design based on the at least one specified safety property and the set boundaries, executing a formal verification tool on the logic cone to verify the at least one specified property, extending the boundary of the logic cone according to a configurable structural design criterion and performing the extracting and executing on the new logic cone, if the verification result does not satisfy the at least one safety property.
摘要翻译：一种用于执行电子电路设计中的属性的形式验证的改进方法包括：在寄存器传送级别指定电子电路设计中的至少一个安全属性，根据可配置的方式将逻辑锥的边界设置为起始级别结构设计标准，基于至少一个指定的安全属性和设定的边界，从电子电路设计中提取逻辑锥，在逻辑锥上执行形式验证工具，以验证至少一个指定的属性，根据可配置结构设计标准的逻辑锥，并且如果验证结果不满足至少一个安全属性，则执行在新的逻辑锥上的提取和执行。

2. 发明授权

US08589327B2 Efficiently determining boolean satisfiability with lazy constraints 失效
标题翻译：有效地确定具有延迟约束的布尔可满足性
公开(公告)号：US08589327B2
公开(公告)日：2013-11-19
申请号：US13092262
申请日：2011-04-22
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/00 , G06N5/02
CPC分类号： G06F17/504 , G06F17/11 , G06F2217/06
摘要： A mechanism is provided for efficiently determining Boolean satisfiability (SAT) using lazy constraints. A determination is made as to whether a SAT problem is satisfied without constraints in a list of constraints. Responsive to the SAT problem being satisfied without constraints, a set of variable assignments that are determined in satisfying the SAT problem without constraints are fixed. For each constraint in the list of constraints, a determination is made as to whether the SAT problem with the constraint results in the set of variable assignments remaining constant. Responsive to the SAT problem with the constraint resulting in the set of variable assignments remaining constant, the constraint is added to a list of non-affecting constraints and a satisfied result is returned.
摘要翻译：提供了一种使用延迟约束有效地确定布尔可满足性（SAT）的机制。确定SAT问题是否满足约束列表中的约束。响应于没有约束的满足SAT问题的SAT问题，在不受约束的情况下满足SAT问题确定的一组可变分配是固定的。对于约束列表中的每个约束，确定具有约束的SAT问题是否导致可变分配集合保持不变。响应于导致变量赋值集合保持不变的约束的SAT问题，约束被添加到不受影响的约束的列表，并且返回满意的结果。

3. 发明授权

US08473882B2 Method and system for scalable reduction in registers with SAT-based resubstitution 失效
标题翻译：用于基于SAT重新配置的寄存器的可缩减方法和系统
公开(公告)号：US08473882B2
公开(公告)日：2013-06-25
申请号：US13415924
申请日：2012-03-09
申请人： Jason R. Baumgartner , Michael L. Case , Hari Mony , Viresh Paruthi
发明人： Jason R. Baumgartner , Michael L. Case , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/505
摘要： A method, system, and computer program product for reducing the size of a logic network design, prior to verification of the logic network design. The method includes eliminating registers to reduce the size of the logic network design; thereby, increasing the speed and functionality of the verification process, and decreasing the size of the logic network design. The system identifies one or more compatible resubstitutions of a selected register, wherein the compatible resubstitution expresses the selected register as one or more pre-existing registers of fixed initial state. The resubstitutions are refined utilizing design invariants. When one more resubstitutions are preformed, the system eliminates the selected registers to reduce the size of the logic network design. As a result of the resubstitution process, a logic network design of reduced size is generated.
摘要翻译：在验证逻辑网络设计之前，用于减小逻辑网络设计大小的方法，系统和计算机程序产品。该方法包括消除寄存器以减小逻辑网络设计的大小; 从而增加验证过程的速度和功能，并减小逻辑网络设计的大小。系统识别所选择的寄存器的一个或多个兼容的重新配置，其中兼容重新配置将所选择的寄存器表示为一个或多个预先存在的固定初始状态的寄存器。利用设计不变量来改进重组。当再进行一次重新配置时，系统将删除所选择的寄存器以减小逻辑网络设计的大小。作为重新配置处理的结果，生成尺寸减小的逻辑网络设计。

4. 发明授权

US08418106B2 Techniques for employing retiming and transient simplification on netlists that include memory arrays 失效
标题翻译：对包含存储器阵列的网表进行重新定时和瞬态简化的技术
公开(公告)号：US08418106B2
公开(公告)日：2013-04-09
申请号：US12872490
申请日：2010-08-31
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A technique for performing an analysis of a logic design (that includes a native memory array embodied in a netlist) includes detecting an initial transient behavior in the logic design as embodied in the netlist. The technique also includes determining a duration of the initial transient behavior and gathering reduction information on the logic design based on the initial transient behavior. The netlist is then modified based on the reduction information.
摘要翻译：用于执行对逻辑设计（包括在网表中包含的本地存储器阵列）的分析的技术包括检测在网表中体现的逻辑设计中的初始瞬态行为。该技术还包括基于初始瞬态行为来确定初始瞬态行为的持续时间并收集关于逻辑设计的减少信息。然后基于减少信息来修改网表。

5. 发明申请

US20120290992A1 LOGICAL CIRCUIT NETLIST REDUCTION AND MODEL SIMPLIFICATION USING SIMULATION RESULTS CONTAINING SYMBOLIC VALUES 失效
标题翻译：使用包含符号值的模拟结果的逻辑电路网络列表减少和模型简化
公开(公告)号：US20120290992A1
公开(公告)日：2012-11-15
申请号：US13104573
申请日：2011-05-10
申请人： Michael L. Case , Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony
发明人： Michael L. Case , Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A logic synthesis program, method and system for simplifying and/or reducing a logic design receives output from a logic simulator that uses symbolic values for stimulus and contains symbolic values in the logic simulator output. Relationships between the nodes dependent on symbolic values can be used to merge nodes or otherwise simplify the logic design. Behaviors such as oscillators, transient values, identical signals, dependent logical states and chicken-switch determined states that depend on the symbolic values can be detected in the simulation results and the netlist simplified using the results of the detection. The netlist can be simplified by inserting registers to represent nodes that assume a symbolic value or combination based on symbolic values either statically or after an initial transient. Oscillating nodes can be replaced with equivalent oscillator circuits, and nodes having values dependent on chicken-switch operation can be detected and replaced with registers initialized from the chicken-switch input states.
摘要翻译：用于简化和/或减少逻辑设计的逻辑综合程序，方法和系统从逻辑模拟器接收输出，该逻辑模拟器使用符号值作为刺激，并在逻辑模拟器输出中包含符号值。依赖于符号值的节点之间的关系可用于合并节点或简化逻辑设计。可以在仿真结果和使用检测结果简化的网表中检测到依赖于符号值的振荡器，瞬态值，相同信号，依赖逻辑状态和鸡开关确定状态等行为。可以通过插入寄存器来简化网表，以代表以静态方式或初始瞬态之后基于符号值假设符号值或组合的节点。振荡节点可以用等效的振荡器电路代替，并且可以检测具有取决于鸡开关操作的值的节点，并用从鸡开关输入状态初始化的寄存器替换振荡节点。

6. 发明申请

US20120192133A1 LOGIC DESIGN VERIFICATION TECHNIQUES FOR LIVENESS CHECKING WITH RETIMING 有权
标题翻译：用于生活垃圾检查的LOGIC设计验证技术
公开(公告)号：US20120192133A1
公开(公告)日：2012-07-26
申请号：US13436196
申请日：2012-03-30
申请人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
发明人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned.
摘要翻译：用于使用活动检查验证重新定时逻辑设计的技术包括将活跃门分配给原始网表的活动属性，并将公平门分配给原始网表的公平约束。在这种情况下，公平门与活跃门相关联，并且在与活跃门相关联的任何有效行为循环期间被断言至少一个时间步长。使用重新定时引擎重新计算原始网表，以提供重新定时的网表。重新定义的网表的活跃和公平的门被重新定位，使得公平门的滞后不大于活跃门的滞后。然后在重新定时的网表上进行验证分析。最后，当验证分析为重新定时的网表产生有效的对照示例时，返回原始网表的活动违反。

7. 发明授权

US08146034B2 Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays. 有权
标题翻译：有效的冗余识别，冗余删除和在包括内存数组的设计中的顺序等价检查。
公开(公告)号：US08146034B2
公开(公告)日：2012-03-27
申请号：US12771677
申请日：2010-04-30
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A mechanism is provided for efficient redundancy identification, redundancy removal, and sequential equivalence checking with designs including memory arrays. The mechanism includes an array merging component to optimally merge an array output such that if the address is out-of-bounds or the port is not asserted, the array output is converted to a random output. The mechanism also includes a component for determining the equivalence of enabled array outputs rather than the array outputs directly and creating an enabled array output. The mechanism also includes a component that precludes potentially-redundant array cells from participating in the sequential redundancy removal determination. This component first checks for compatibility of the corresponding arrays, then the corresponding read port enables and addresses, then the corresponding initial values, and finally checking that writes to the corresponding columns yield a compatible set of values.
摘要翻译：提供了一种机制，用于有效的冗余识别，冗余删除和与包括存储器阵列的设计的顺序等同性检查。该机制包括阵列合并组件，以最佳地合并阵列输出，以便如果地址超出边界或端口未被断言，阵列输出将转换为随机输出。该机制还包括用于确定启用的阵列输出的等效性的组件，而不是直接对阵列输出进行创建并创建启用的阵列输出。该机制还包括排除潜在冗余阵列单元参与顺序冗余移除确定的组件。该组件首先检查相应阵列的兼容性，然后对应的读端口启用和地址，然后对应的初始值，最后检查对相应列的写入是否产生兼容的值集合。

8. 发明授权

US08122403B2 Trace containment detection of combinational designs via constraint-based uncorrelated equivalence checking 有权
标题翻译：通过基于约束的不相关等价检查的组合设计的跟踪容限检测
公开(公告)号：US08122403B2
公开(公告)日：2012-02-21
申请号：US12425095
申请日：2009-04-16
申请人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
发明人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504
摘要： Methods and systems are provided for producing more efficient digital circuitry designs by identifying trace-containment for a sequential circuitry design netlist through the use of constraint-based uncorrelated equivalence checking. A set of candidate input netlist sets n1 and n2 is first uncorrelated and then submitted for equivalence checking. Mismatches discovered during the equivalence checking are avoided by imposing constraint to the input set until discovering an equivalency relationship between the input sets n1 and n2.
摘要翻译：提供了方法和系统，用于通过使用基于约束的不相关等价检查来识别顺序电路设计网表的跟踪容纳来产生更有效的数字电路设计。一组候选输入网表集n1和n2首先不相关，然后提交用于等价检查。在等效检查期间发现的不匹配通过对输入集施加约束来避免，直到发现输入集n1和n2之间的等价关系。

9. 发明授权

US08086429B2 Predicate-based compositional minimization in a verification environment 失效
标题翻译：在验证环境中基于谓词的组合最小化
公开(公告)号：US08086429B2
公开(公告)日：2011-12-27
申请号：US12168469
申请日：2008-07-07
申请人： Jason R. Baumgartner , Hari Mony , Viresh Paruthi , Fadi A. Zaraket
发明人： Jason R. Baumgartner , Hari Mony , Viresh Paruthi , Fadi A. Zaraket
IPC分类号： G06F17/50 , G06F7/44
CPC分类号： G06F17/504
摘要： A system for performing verification includes a means for: importing a design netlist containing component(s), computing output function(s) for the component(s), generating output equivalent state set(s) from the output function(s), identifying next-state function(s) for the component(s), means for producing image equivalent state set(s) for the next-state function(s), means for classifying output-and-image equivalent state set(s) for the image equivalent state set(s) and the output equivalent state set(s), getting a preimage from the next-state function(s) and the output-and-image equivalent state(s) to generate a preimage of the output-and-image equivalent state(s), partitioning over original state(s) of the component(s), and equivalent class input set(s) of the component(s). Moreover, the system includes a means for: selecting input representative(s) of the equivalent input set(s), forming an input map from the input representative(s), synthesizing the input map, and injecting the input map back into the netlist to generate a modified netlist.
摘要翻译：用于执行验证的系统包括用于：导入包含组件的设计网表，计算组件的计算输出功能，从输出功能生成输出等效状态集合的装置，识别用于组件的下一状态功能，用于产生用于下一状态功能的图像等价状态集合的装置，用于对用于下一状态功能的输出和图像等效状态集合进行分类的装置图像等效状态集合和输出等效状态集合，从下一状态函数获得预图像和输出和图像等效状态以生成输出的前图像，以及图像等效状态，对组件的原始状态进行分区，以及组件的等效类输入集合。此外，该系统包括一种装置，用于：选择等效输入组的输入代表，从输入代表形成输入图，合成输入图，并将输入图反映回网表中以生成修改的网表。

10. 发明授权

US07856609B2 Using constraints in design verification 有权
标题翻译：在设计验证中使用约束
公开(公告)号：US07856609B2
公开(公告)日：2010-12-21
申请号：US12164781
申请日：2008-06-30
申请人： Jason R. Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
发明人： Jason R. Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/504
摘要： A method for generating a constraint for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which the identified target may be asserted. A constraint space C′ is then derived from the state space S′, where C′ is the logical complement of S′. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate.
摘要翻译：用于生成用于生成用于集成电路设计的验证的约束的约束的方法包括识别所述设计的网表（N）中的目标并且创建所述网表的过近似抽象（N'）。通过枚举从其识别出的目标可以被断言的N'的状态来创建空间状态（S'）。然后从状态空间S'导出约束空间C'，其中C'是S'的逻辑补码。对于多个选定的目标重复该过程，并且来自每个迭代的约束空间被逻辑地进行AND。创建过近似抽象可能包括用随机门替换顺序门。识别顺序门可以包括选择网表中的目标，执行目标的近似不正确的验证，并且如果发生虚假故障，则选择进一步向下沿当前选择的门的扇形链的门。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式