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2. 发明专利

JP5155843B2 Information processing apparatus and a neural network circuit using the same 有权
公开(公告)号：JP5155843B2
公开(公告)日：2013-03-06
申请号：JP2008326313
申请日：2008-12-22
申请人：シャープ株式会社 , 隆森江
发明人：茂夫大西 , 隆森江
IPC分类号： G06G7/60 , G06N3/063
CPC分类号： G11C11/54 , G06N3/063 , G11C13/0002

3. 发明专利

JP2009282782A Product arithmetic unit including resistance change type variable resistor element, product sum arithmetic unit, neural network providing each neuron element with these arithmetic units, and product arithmetic method 有权
标题翻译：产品算术单元，包括电阻变化型变量电阻元件，产品单位算术单元，提供每个具有这些算术单位的神经元元素的神经网络和产品算术方法
公开(公告)号：JP2009282782A
公开(公告)日：2009-12-03
申请号：JP2008134682
申请日：2008-05-22
申请人： Takashi Morie , Sharp Corp , シャープ株式会社 , 隆森江
发明人： ONISHI SHIGEO , ISHIHARA KAZUYA , MORIE TAKASHI
IPC分类号： G06N3/063
摘要： PROBLEM TO BE SOLVED: To simplify configurations of a product arithmetic unit and a product sum arithmetic unit and to reduce occupied areas of the product arithmetic unit and the product sum arithmetic unit in the area of the whole circuit including these units. SOLUTION: When a single voltage pulse of pulse width Ti corresponding to a multiplicand is input to a terminal A of the resistance change type variable resistor element 1 having terminals A, B and a voltage pulse string of a pulse frequency Fi corresponding to a multiplier is input to the terminal B, a PWM (pulse width modulation) signal according to the Fi, Ti corresponding to a product operation result between the multiplicand and the multiplier is output. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了简化产品运算单元和乘积和运算单元的配置，并且在包括这些单元的整个电路的区域中减少乘积运算单元和乘积和运算单元的占用面积。解决方案：当对应于被乘数的脉冲宽度Ti的单个电压脉冲被输入到具有端子A，B的电阻变化型可变电阻器元件1的端子A和与之相对应的脉冲频率Fi的电压脉冲串时向终端B输入乘法器，输出与乘法器和乘法器之间的乘积运算结果对应的根据Fi，Ti的PWM（脉宽调制）信号。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2003044850A Method and device for extracting image area 审中-公开
标题翻译：提取图像区域的方法和装置
公开(公告)号：JP2003044850A
公开(公告)日：2003-02-14
申请号：JP2001232964
申请日：2001-07-31
申请人： Atsushi Iwata , Takashi Morie , 穆岩田 , 隆森江
发明人： MORIE TAKASHI , NAKANO TEPPEI , IWATA ATSUSHI , NAGATA MAKOTO
IPC分类号： G06T1/20 , G06T7/00
摘要： PROBLEM TO BE SOLVED: To make an area extraction function easily includable in a circuit for acquiring area boundary information in pixel parallel processing by providing a method for sequentially and fast extracting closed areas defined on the basis of area boundary pixel information at temporally different timing and a device composed of a circuit for performing the method.
SOLUTION: Image edge pixels and area boundary pixels are set in a first state with respect to an image with an area boundary given, pixels other than the image edge pixels and area boundary pixels are set in a second state, one optional pixel in the second state is next set in a third state, if any among adjacent pixels is in the third state with respect to the whole pixels in the second state, processing that changes the pixel to be in the third state is repeated, the position information of the pixel in the third state is outputted when pixels to be changed do not exist any more, the pixel in the third state is subsequently made to be in the first state, and these series of processing are repeated until the pixels in the second state do not exist any more.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：通过提供一种在时间上不同的定时提供基于区域边界像素信息定义的闭合区域的方法，通过提供用于获取像素并行处理中的区域边界信息的电路中容易地包括区域提取功能，以及由用于执行该方法的电路组成的装置。解决方案：图像边缘像素和区域边界像素相对于给定面积边界的图像被设置在第一状态中，除了图像边缘像素和区域边界像素之外的像素被设置在第二状态，第二状态中的一个可选像素下一个状态被设置在第三状态中，如果相邻像素中的任一个相对于第二状态下的整个像素处于第三状态，则重复改变为处于第三状态的像素的处理，则像素的位置信息在不再存在要改变的像素的情况下输出第三状态，随后使第三状态的像素处于第一状态，并且重复这些系列处理，直到不存在第二状态的像素再说了

5. 发明专利

JP2003044840A Information processing circuit 审中-公开
标题翻译：信息处理电路
公开(公告)号：JP2003044840A
公开(公告)日：2003-02-14
申请号：JP2001232965
申请日：2001-07-31
申请人： Atsushi Iwata , Takashi Morie , 穆岩田 , 隆森江
发明人： MORIE TAKASHI , MIYAKE MAKOTO , IWATA ATSUSHI , NAGATA MAKOTO
IPC分类号： G06T1/20
摘要： PROBLEM TO BE SOLVED: To provide a circuit for generating a pulse width modulation signal or a pulse phase modulation signal representing the difference between two analog values and to provide also a processing unit circuit which is of a small area and power saving and is fast in an image processing system characterized in applying the circuit to image processing and making a pixel parallel operation type processing unit update a state by an operation with an adjacent pixel processing unit.
SOLUTION: A binary signal representing the magnitude relation of two voltages and the pulse width modulation signal or pulse phase modulation signal having information of the absolute value of the difference between the two voltages are generated by holding two analog voltages in two capacitors and serially connecting the capacitors. Also, a subtraction circuit is sued for an image processing unit circuit to convert results operated on the basis of information of adjacent pixels as an analog voltage into a pulse phase modulation signal, and a nonlinear current source is switched with the signal to update a self-state.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种用于产生表示两个模拟值之间的差的脉宽调制信号或脉冲相位调制信号的电路，并且还提供一种处理单元电路，该电路具有小的面积和功率节省并且快速一种图像处理系统，其特征在于将电路应用于图像处理，并使像素并行操作类型处理单元通过与相邻像素处理单元的操作更新状态。解决方案：表示两个电压的幅度关系的二进制信号和具有两个电压差的绝对值的信息的脉宽调制信号或脉冲相位调制信号是通过在两个电容器中保持两个模拟电压而产生的，并且串联连接电容器此外，为了将图像处理单元电路的减法电路转换为根据作为模拟电压的相邻像素的信息而进行操作的结果，转换为脉冲相位调制信号，并且用信号切换非线性电流源来更新自身 -州。

6. 发明专利

JP2010146514A Information processor and neural network circuit using the same 有权
标题翻译：信息处理器和使用相同的神经网络电路
公开(公告)号：JP2010146514A
公开(公告)日：2010-07-01
申请号：JP2008326313
申请日：2008-12-22
申请人： Takashi Morie , Sharp Corp , シャープ株式会社 , 隆森江
发明人： ONISHI SHIGEO , MORIE TAKASHI
IPC分类号： G06G7/60 , G06N3/063
CPC分类号： G11C11/54 , G06N3/063 , G11C13/0002
摘要： PROBLEM TO BE SOLVED: To provide an information processor storing synapse bond strength as an analog quantity without increasing an occupied area on an LSI chip by indicating the synapse bond strength using a resistance value of a resistance variable memory element. SOLUTION: The information processor 100 includes at least one synapse circuit 102. The synapse circuit 102 has the resistance variable memory element 24 reversibly varied by the application of voltage pulses, and an STDP (spike-timing dependent synaptic plasticity) section 25 carrying out operation using a function that indicates a preset nonlinear voltage waveform according to a lag of input timing between two spike pulses input at different timing. The STDP section 25 carries out operation to the lag of the input timing when the two spike pulses are input, and sets a voltage pulse applied to the resistance variable memory element 24 based on the operation result. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过使用电阻可变存储元件的电阻值指示突触结合强度，提供将突触结合强度作为模拟量存储的信息处理器，而不增加LSI芯片上的占用面积。解决方案：信息处理器100包括至少一个突触电路102.突触电路102具有通过施加电压脉冲而可逆地变化的电阻可变存储元件24，以及STDP（尖峰定时依赖性突触可塑性）部分25 根据在不同定时输入的两个尖峰脉冲之间的输入定时的滞后，使用表示预设非线性电压波形的功能进行操作。当输入两个尖峰脉冲时，STDP部25进行输入定时的滞后运算，根据运算结果设定施加到电阻变量存储元件24的电压脉冲。版权所有（C）2010，JPO＆INPIT

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