To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. In the present invention, the following are provided: a semiconductor chip (100) that has first and second pad electrodes (120a, 120b) disposed on the main surface thereof; insulating films (310, 330) that cover the main surface of the semiconductor chip (100); a rewiring layer (320) that is disposed between the insulating films (310, 330); and a plurality of external terminals (340) disposed on the top of the insulating film (330). The plane size of the first pad electrode (120a) and the second pad electrode (120b) differ from one another, and the first pad electrode (120a) and the second pad electrode (120b) are connected to any of the plurality of external terminals (340) via the rewiring layer (320). According to the present invention, because the pad electrodes (120a, 120b) of different sizes are intermixed, probing can be easily performed while reducing the area occupied by the pad electrodes.