Disclosed is a non-volatile semiconductor memory device with which, while effecting miniaturization, occurrence of interference can be suppressed better than the prior art. In this non-volatile semiconductor memory device (1), not only in a selected power supply unit (4a), but also in a non-selected power supply unit (4b), the voltage value of the prohibited write-in gate voltage, the voltage value applied at the current P-type memory well (PW2), and the voltage value of the non-selected first bit line (L1c) and the non-selected second bit line (L2c) voltage value can be freely set to, for example, a voltage value able to suppress occurrence of interference. The respective power supply units (4) are connected by common PMOS control lines (PGa ~ PGd) and common NMOS control lines (NGa ~ NGd). By switching actions of PMOS switches (8a, 8c, ... (8b, 8d, ...)) and NMOS switches (9a, 9c ... (9b, 9d, ...)) according to the voltage values applied to the common PMOS control lines (PGa ~ PGd) and common NMOS control lines (NGa ~ NGd), it is possible to selectively decide the word line (15a) from the entire word lines (15), thereby obviating the need for a separate column address decoder for each word line row (each P-type memory well (PW2)), and allowing effecting miniaturization as in the prior art.