发明专利
TW201241834A 半導體記憶體元件、測試電路、及其測試操作方法 SEMICONDUCTOR MEMORY DEVICE, TEST CIRCUIT, AND TEST OPERATION METHOD THEREOF
审中-公开
基本信息:
- 专利标题： 半導體記憶體元件、測試電路、及其測試操作方法 SEMICONDUCTOR MEMORY DEVICE, TEST CIRCUIT, AND TEST OPERATION METHOD THEREOF
- 专利标题（英）：Semiconductor memory device, test circuit, and test operation method thereof
- 专利标题（中）：半导体内存组件、测试电路、及其测试操作方法 SEMICONDUCTOR MEMORY DEVICE, TEST CIRCUIT, AND TEST OPERATION METHOD THEREOF
- 申请号：TW100149339 申请日：2011-12-28
- 公开(公告)号：TW201241834A 公开(公告)日：2012-10-16
- 发明人： 都昌鎬 , 金演祐
- 申请人： 海力士半導體股份有限公司
- 申请人地址： HYNIX SEMICONDUCTOR INC. 南韓 KR
- 专利权人： 海力士半導體股份有限公司
- 当前专利权人： 海力士半導體股份有限公司
- 当前专利权人地址： HYNIX SEMICONDUCTOR INC. 南韓 KR
- 代理人： 陳長文
- 优先权： 美國 12/982,409 20101230
- 主分类号： G11C
- IPC分类号： G11C
A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells; a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads; a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells during a test mode; and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.
公开/授权文献:
- TWI550623B 半導體記憶體元件、測試電路、及其測試操作方法 公开/授权日：2016-09-21