基本信息:
- 专利标题: LDS - LDS 페인팅 반복 공정을 이용한 다층 회로 형성 방법
- 专利标题(英):Methdo of forming multi-layer curcuit using lds - lds painting repeat process
- 专利标题(中):LDS - 使用LDS绘画重复过程的多层电路形成方法
- 申请号:KR1020160059651 申请日:2016-05-16
- 公开(公告)号:KR1020170129331A 公开(公告)日:2017-11-27
- 发明人: 김효진 , 고우영 , 이진성 , 김영호
- 申请人: (주)드림텍
- 申请人地址: 경기도 성남시 분당구 황새울로 *** (서현동)
- 专利权人: (주)드림텍
- 当前专利权人: (주)드림텍
- 当前专利权人地址: 경기도 성남시 분당구 황새울로 *** (서현동)
- 代理人: 특허법인 대아
- 主分类号: H05K3/46
- IPC分类号: H05K3/46 ; H05K1/03 ; H05K1/09
It discloses with respect to the LDS process and the multi-layered circuit forming method using the LDS painting process.
Multi-layer circuit forming process according to the invention using the injection molding method comprising: (a) producing a molding substrate having a via-hole; Step (b) such that a portion of the first circuit pattern overlaps with the via-holes in the molding substrate, but the first circuit forms a pattern by performing LDS, and plated on the first surface of the molding substrate; (C) forming an insulating layer by coating and drying the LDS coating paint containing a thermoplastic resin on a molded substrate that the first circuit pattern; And (d) the first, but form a second circuit pattern by performing LDS, and plated on an insulating layer, a second circuit part of the pattern that overlaps the portion of the first circuit pattern; And (e) a portion of the first circuit pattern, but the third circuit forming a pattern by performing LDS, and plated on the second side of the molded substrate, a portion of the third circuit pattern through the via-hole of the molding substrate and step to ensure electrical connection with; including, while forming a three or more layers of the circuit is characterized in that using the injection only in the step (a).
信息查询:
EspacenetIPC结构图谱:
H | 电学 |
--H05 | 其他类目不包含的电技术 |
----H05K | 印刷电路;电设备的外壳或结构零部件;电气元件组件的制造 |
------H05K3/00 | 用于制造印刷电路的设备或方法 |
--------H05K3/46 | .多层电路的制造 |