基本信息:
- 专利标题: 반도체 메모리 소자 및 제조방법
- 专利标题(英):Semiconductor device and manufacturing method thereof
- 专利标题(中):半导体器件及其制造方法
- 申请号:KR1020060121512 申请日:2006-12-04
- 公开(公告)号:KR1020080050787A 公开(公告)日:2008-06-10
- 发明人: 박경환 , 최은석 , 김세준 , 유현승
- 申请人: 에스케이하이닉스 주식회사
- 申请人地址: 경기도 이천시 부발읍 경충대로 ****
- 专利权人: 에스케이하이닉스 주식회사
- 当前专利权人: 에스케이하이닉스 주식회사
- 当前专利权人地址: 경기도 이천시 부발읍 경충대로 ****
- 代理人: 신영무
- 主分类号: H01L27/115
- IPC分类号: H01L27/115 ; H01L21/8247
摘要:
A method for manufacturing a semiconductor memory device is provided to prevent the damage of a semiconductor substrate by performing a patterning process for forming a blocking layer after performing an ion implantation process. A tunnel dielectric layer(102), a charge storing layer(104), a blocking dielectric layer(106), and a gate electrode(108) are formed on a semiconductor substrate(100). A first etching process is performed to remove an edge of the blocking dielectric layer. An ion implantation process is performed on the semiconductor substrate. A high-k dielectric layer is formed on an upper portion of the entire structure including a part of which blocking dielectric is removed. A second etching process is performed so that the high-k dielectric layer remains only between the gate pattern and the charge storing layer. The blocking dielectric is formed with one of LPTEOS(Low Pressure Tetra-Ethyl-Ortho-Silicate), HTO(High Temperature Oxide), PE-USG(Undoped Silicate Glass), or an oxide nitride layer. A thickness of the blocking dielectric layer is 50 to 1000 Å.
摘要(中):
提供一种制造半导体存储器件的方法,用于通过在执行离子注入工艺之后执行用于形成阻挡层的图案化工艺来防止半导体衬底的损坏。 在半导体衬底(100)上形成隧道介电层(102),电荷存储层(104),阻挡介质层(106)和栅电极(108)。 执行第一蚀刻工艺以去除阻挡电介质层的边缘。 在半导体衬底上进行离子注入工艺。 在整个结构的上部形成有高k电介质层,其中包括去除阻挡电介质的一部分。 执行第二蚀刻工艺,使得高k电介质层仅保留在栅极图案和电荷存储层之间。 阻挡电介质由LPTEOS(低压四乙基 - 正硅酸盐),HTO(高温氧化物),PE-USG(未掺杂的硅酸盐玻璃)或氧化物氮化物层之一形成。 阻挡电介质层的厚度为50〜1000。
公开/授权文献:
- KR101005638B1 반도체 메모리 소자 및 제조방법 公开/授权日:2011-01-05
信息查询:
EspacenetIPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L27/00 | 由在一个共用衬底内或其上形成的多个半导体或其他固态组件组成的器件 |
--------H01L27/02 | .包括有专门适用于整流、振荡、放大或切换的半导体组件并且至少有一个电位跃变势垒或者表面势垒的;包括至少有一个跃变势垒或者表面势垒的无源集成电路单元的 |
----------H01L27/04 | ..其衬底为半导体的 |
------------H01L27/06 | ...在非重复结构中包括有多个单个组件的 |
--------------H01L27/105 | ....包含场效应组件的 |
----------------H01L27/112 | .....只读存储器结构的 |
------------------H01L27/115 | ......电动编程只读存储器 |