基本信息:
- 专利标题: 듀얼 포트 반도체 메모리 장치
- 专利标题(英):Semiconductor memory device including a dual port
- 专利标题(中):具有双端口的半导体存储器件
- 申请号:KR1020030006365 申请日:2003-01-30
- 公开(公告)号:KR1020040069823A 公开(公告)日:2004-08-06
- 发明人: 이태정 , 김병선 , 이준형
- 申请人: 삼성전자주식회사
- 申请人地址: ***, Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, Republic of Korea
- 专利权人: 삼성전자주식회사
- 当前专利权人: 삼성전자주식회사
- 当前专利权人地址: ***, Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, Republic of Korea
- 代理人: 리앤목특허법인
- 主分类号: G11C5/02
- IPC分类号: G11C5/02
摘要:
PURPOSE: A semiconductor memory device provided with a dual port is provided to improve the electrical characteristics of the semiconductor memory device by increasing the noise margin in comparison with the semiconductor memory device. CONSTITUTION: A semiconductor memory device provided with a dual port includes a semiconductor substrate provided with a plurality of memory cells, a word line and scan address line, a pair of bitlines and a scan data outline. Each of the memory cells is provided with a first CMOS inverter, a second CMOS inverter, a third NMOS transistor(N3), a fourth NMOS transistor(N4) and a third PMOS transistor(P3). The first CMOS inverter includes a first NMOS transistor(N1), a first PMOS transistor(P1), an input terminal and an output transistor. The second CMOS inverter includes a second NMOS transistor(N2), a second PMOS transistor(P2), an input terminal and an output terminal. The gate of the third NMOS transistor(N3) is connected to the word line, the drain of the third NMOS transistor(N3) is connected to the bitline and the source of the third NMOS transistor(N3) is connected to the second memory node. The gate of the fourth NMOS transistor(N4) is connected to the word line, the drain of the fourth NMOS transistor(N4) is connected to the complementary bitline and the source of the fourth NMOS transistor(N4) is connected to the second memory node. And, the gate of the third PMOS transistor(P3) is connected to the scan address line and the source of the third PMOS transistor(P3) is connected to the second memory node.
摘要(中):
目的:提供一种设置有双端口的半导体存储器件,用于通过增加与半导体存储器件相比的噪声容限来改善半导体存储器件的电特性。 构成:设置有双端口的半导体存储器件包括设置有多个存储单元的半导体衬底,字线和扫描地址线,一对位线和扫描数据轮廓。 每个存储单元设置有第一CMOS反相器,第二CMOS反相器,第三NMOS晶体管(N3),第四NMOS晶体管(N4)和第三PMOS晶体管(P3)。 第一CMOS反相器包括第一NMOS晶体管(N1),第一PMOS晶体管(P1),输入端子和输出晶体管。 第二CMOS反相器包括第二NMOS晶体管(N2),第二PMOS晶体管(P2),输入端子和输出端子。 第三NMOS晶体管(N3)的栅极连接到字线,第三NMOS晶体管(N3)的漏极连接到位线,并且第三NMOS晶体管(N3)的源极连接到第二存储器节点 。 第四NMOS晶体管(N4)的栅极连接到字线,第四NMOS晶体管(N4)的漏极连接到互补位线,并且第四NMOS晶体管(N4)的源极连接到第二存储器 节点。 并且,第三PMOS晶体管(P3)的栅极连接到扫描地址线,并且第三PMOS晶体管(P3)的源极连接到第二存储器节点。
公开/授权文献:
- KR100539229B1 듀얼 포트 반도체 메모리 장치 公开/授权日:2005-12-27
信息查询:
EspacenetIPC结构图谱:
G | 物理 |
--G11 | 信息存储 |
----G11C | 静态存储器 |
------G11C5/00 | 包括在G11C11/00组中的存储器零部件 |
--------G11C5/02 | .存储元件的排列,例如,矩阵形式的排列 |