基本信息:
- 专利标题: 반도체 패키지
- 专利标题(英):Semiconductor package
- 专利标题(中):半导体封装
- 申请号:KR1020150017324 申请日:2015-02-04
- 公开(公告)号:KR101640341B1 公开(公告)日:2016-07-15
- 发明人: 김근수 , 박철우 , 유동수 , 김재윤 , 강대병 , 안병준
- 申请人: 앰코 테크놀로지 코리아 주식회사
- 申请人地址: 광주광역시 북구 앰코로 *** (대촌동)
- 专利权人: 앰코 테크놀로지 코리아 주식회사
- 当前专利权人: 앰코 테크놀로지 코리아 주식회사
- 当前专利权人地址: 광주광역시 북구 앰코로 *** (대촌동)
- 代理人: 서만규; 서경민
- 主分类号: H01L23/00
- IPC分类号: H01L23/00 ; H01L23/488 ; H01L23/28
The present invention relates to a semiconductor package, which improves the reliability and reduces the phenomenon Wars page.
In one example, the insulating layer and the circuit board includes a second wiring pattern formed on a lower surface of the insulating the first wiring pattern formed on the upper surface of the layer and the insulating layer, seated on an upper surface of the circuit board, the semiconductor die, said circuit board encapsulating the semiconductor die, on top of and wa teu of kaepsyulran through vias are formed exposing the first wiring pattern to the outside, is formed in the through via-containing electrically conductive bump connected to the first wiring pattern wherein semiconductor device; It is seated on an upper portion of the semiconductor device, insulator and an interposer including a solder ball formed on the wiring pattern and the wiring pattern formed on the lower face of the insulator; And the semiconductor device and the interlayer member interposed between the interposer; includes, the solder ball is disclosed a semiconductor package, characterized in that electrically connected to the conductive bump.
信息查询:
EspacenetIPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L23/00 | 半导体或其他固态器件的零部件 |