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1. 发明授权

KR101640341B1 반도체 패키지 有权
标题翻译：半导体封装
公开(公告)号：KR101640341B1
公开(公告)日：2016-07-15
申请号：KR1020150017324
申请日：2015-02-04
申请人： 앰코 테크놀로지 코리아 주식회사
发明人： 김근수 , 박철우 , 유동수 , 김재윤 , 강대병 , 안병준
IPC分类号： H01L23/00 , H01L23/488 , H01L23/28
CPC分类号： H01L23/49894 , H01L23/3121 , H01L23/42 , H01L23/433 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/5389 , H01L25/105 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/92225 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/15311 , H01L2924/1533 , H01L2924/18161 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L24/97 , H01L23/28 , H01L23/488 , H01L23/522
摘要： 본발명은신뢰성을향상시키고워페이지현상을줄일수 있는반도체패키지에관한것이다. 일례로, 절연층과상기절연층의상면에형성된제 1 배선패턴과상기절연층의하면에형성된제 2 배선패턴을포함하는회로기판과, 상기회로기판의상면에안착된반도체다이와, 상기회로기판의상부에서상기반도체다이를인캡슐레이션하며상기제 1 배선패턴을외부로노출시키는관통비아가형성된인캡슐란트와, 상기관통비아에형성되며상기제 1 배선패턴에전기적으로연결된도전성범프를포함하는반도체디바이스; 상기반도체디바이스의상부에안착되며, 절연체와상기절연체의하면에형성된배선패턴과상기배선패턴에형성된솔더볼을포함하는인터포저; 및상기반도체디바이스와상기인터포저사이에개재된층간부재;를포함하고, 상기솔더볼은상기도전성범프에전기적으로연결된것을특징으로하는반도체패키지를개시한다.
摘要翻译：本发明涉及能够提高可靠性并减少翘曲现象的半导体封装。作为示例，公开了半导体封装。半导体封装包括：半导体器件，其包括电路板，其包括绝缘层，形成在绝缘层的上表面上的第一布线图案和形成在绝缘层的下表面上的第二布线图案，半导体管座在所述电路板的上表面上，封装有将所述半导体管芯封装在所述电路基板的上部，并具有从所述第一布线图案外部暴露的贯通孔以及电连接到所述第一布线图案的导电凸块; 安置在半导体器件的上部的插入件，并且包括绝缘体，形成在绝缘体的下表面上的布线图案和形成在绝缘体的下表面上的焊球; 以及插入在所述半导体器件和所述插入件之间的中间层构件。焊球与导电凸块电连接。

2. 发明公开

KR1020160018628A 싱귤레이티드 유닛 서브스트레이트를 이용한 반도체 디바이스 및 그 제조 방법 审中-实审
标题翻译：使用复合单元基板的半导体器件及其制造方法
公开(公告)号：KR1020160018628A
公开(公告)日：2016-02-17
申请号：KR1020160010949
申请日：2016-01-28
申请人： 앰코 테크놀로지 코리아 주식회사
发明人： 김근수 , 안병준 , 이춘흥 , 김진영 , 강대병 , 세인트아만드로저
IPC分类号： H01L21/78 , H01L21/56 , H01L23/00 , H01L23/488
CPC分类号： H01L21/78 , H01L21/56 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/95 , H01L2224/131 , H01L2224/13147 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/83005 , H01L2224/83104 , H01L2224/92125 , H01L2224/95 , H01L2224/95001 , H01L2924/15311 , H01L2224/81 , H01L2224/83 , H01L2924/00014 , H01L2924/014
摘要： 본발명의일 실시예는반도체디바이스및 그제조방법에관한것으로, 해결하고하고자하는기술적과제는양품의싱귤레이티드유닛서브스트레이트만을이용하여반도체디바이스를제조함으로써제조수율을향상시키는데있다. 이를위해본 발명은상면및 하면에형성된회로패턴을포함하는싱귤레이티드유닛서브스트레이트; 상기싱귤레이티드유닛서브스트레이트의상면에접속된반도체다이; 및, 상기반도체다이를인캡슐레이션하고, 상기싱귤레이티드유닛서브스트레이트의상면을덮는인캡슐란트를포함하고, 상기싱귤레이티드유닛서브스트레이트의상면및 하면사이의상기싱귤레이티드유닛서브스트레이트의측면이상기인캡슐란트의측면과동일한평면이되도록절단된반도체디바이스및 그제조방법을개시한다.
摘要翻译：本发明的实施例涉及半导体器件及其制造方法。要解决的技术问题是通过仅使用作为优质产品的单片化单元基板来制造半导体器件来提高制造成品率。根据本发明，公开了半导体器件及其制造方法。半导体器件包括：单片化单元衬底，其包括在单个化单元衬底的顶表面和底表面上的电路图案; 半导体管芯，其结合到单位基板的上表面; 以及密封剂，其被配置为封装所述半导体管芯并覆盖所述单个化单元衬底的顶表面。单片基板的顶表面和底表面之间的单个单元基板的侧表面被切割成与密封剂的侧表面共面。

3. 发明公开

KR1020150089349A 반도체 패키지 및 그 제조 방법 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：KR1020150089349A
公开(公告)日：2015-08-05
申请号：KR1020140009848
申请日：2014-01-27
申请人： 앰코 테크놀로지 코리아 주식회사
发明人： 김근수 , 박철우 , 유동수 , 김재윤 , 강대병 , 안병준
IPC分类号： H01L23/48 , H01L23/12
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/1533 , H01L2924/15331 , H01L2924/18161 , H01L23/48 , H01L23/12 , H01L2924/00
摘要： 본발명은신뢰성을향상시키고워페이지현상을줄일수 있는반도체패키지및 그제조방법에관한것이다. 일례로, 절연층과상기절연층의상면에형성된제 1 배선패턴과상기절연층의하면에형성된제 2 배선패턴을포함하는회로기판과, 상기회로기판의상면에안착된반도체다이와, 상기회로기판의상부에서상기반도체다이를인캡슐레이션하며상기제 1 배선패턴을외부로노출시키는관통비아가형성된인캡슐란트와, 상기관통비아에형성되며상기제 1 배선패턴에전기적으로연결된도전성범프를포함하는반도체디바이스; 상기반도체디바이스의상부에안착되며, 절연체와상기절연체의하면에형성된배선패턴과상기배선패턴에형성된솔더볼을포함하는인터포저; 및상기반도체디바이스와상기인터포저사이에개재된층간부재;를포함하고, 상기솔더볼은상기도전성범프에전기적으로연결되며, 상기층간부재는상기도전성범프와상기솔더볼을감싸도록형성된것을특징으로하는반도체패키지를개시한다.
摘要翻译：本发明涉及能够提高可靠性和降低翘曲的半导体封装及其制造方法。作为示例，半导体封装包括半导体器件，其包括电路板，其包括绝缘层，形成在绝缘层的上侧的第一线图案和形成在绝缘层的下侧上的第二线图案，安装在电路板的上侧的半导体管芯，将半导体管芯封装在电路板的上部并具有用于将第一线路图案暴露于外部的通孔的密封剂，以及导电凸块，其是形成在所述通孔中，并且电连接到所述第一线图案; 安装在半导体器件的上部并且包括绝缘体，形成在绝缘体的下侧的线图案和形成在线图案上的焊球的插入器; 以及插入在所述半导体器件和所述插入件之间的中间部件。焊球与导电凸块电连接。层间构件围绕导电凸块和焊球。

4. 发明授权

KR101404463B1 웨이퍼 지지장치를 이용한 웨이퍼 접합 및 분리 방법 有权
标题翻译：用于使用该方法来结合和去除波浪的波浪支撑系统和方法
公开(公告)号：KR101404463B1
公开(公告)日：2014-06-10
申请号：KR1020130012701
申请日：2013-02-05
申请人： 앰코 테크놀로지 코리아 주식회사
发明人： 엄명철 , 박두현 , 도원철 , 김근수 , 강대병 , 서성민
IPC分类号： H01L21/683
摘要： The present invention relates to a wafer support device and a method for bonding and debonding a wafer using the same and, more specifically, to a wafer support device and a method for bonding and debonding a wafer using the same which bond the wafer on a wafer support of the wafer support device, perform a process such as back grinding, and then easily debond the wafer from the wafer support. The present invention provides the wafer support device and the method for bonding and debonding the wafer using the same, which perforate a plurality of debonding holes on the wafer support, apply an adhesive on the support, bond the wafer on the support, and easily intrude a debonding tool (a chemical solution, air, heating, etc.) into a bottom part of the wafer via the debonding holes, thereby easily debonding the wafer from the wafer support.
摘要翻译：本发明涉及一种晶片支撑装置及其使用其的晶片的接合和剥离方法，更具体地说，涉及一种晶片支撑装置以及使用该晶片将晶片接合在晶片上的晶片的接合和剥离的方法支撑晶片支撑装置，执行诸如背面研磨的处理，然后容易地从晶片支撑件脱离晶片。本发明提供了晶片支撑装置和使用该晶片支撑装置的晶片支撑装置和使其分离的方法，其在晶片支架上穿孔多个脱粘孔，在支撑件上施加粘合剂，将晶片粘结在支撑体上，并容易地侵入脱粘工具（化学溶液，空气，加热等）通过脱粘孔进入晶片的底部，从而容易地从晶片支撑体上脱落晶片。

5. 发明公开

KR1020090021452A 반도체 패키지 有权
标题翻译：半导体封装
公开(公告)号：KR1020090021452A
公开(公告)日：2009-03-04
申请号：KR1020070085974
申请日：2007-08-27
申请人： 앰코 테크놀로지 코리아 주식회사
发明人： 박동주 , 강대병 , 박성순 , 김진성 , 전익수 , 김재동 , 강동희 , 최호
IPC分类号： H01L23/12
CPC分类号： H01L23/552 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32265 , H01L2224/48195 , H01L2224/48227 , H01L2224/48265 , H01L2224/73253 , H01L2224/73265 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15159 , H01L2924/15311 , H01L2924/181 , H01L2924/19103 , H01L2924/19105 , H01L2924/19106 , H01L2924/3025 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor package is provided to improve the stable stack-up structure of the system in package and the electromagnetic interference shielding and the package size reduction structure. A cavity is formed in the chip adhesion area of a substrate(20). A passive device(14) is mounted in the outside location of the chip adhesion area. The cavity is covered by a metal plate(32) for the electromagnetic interference shielding. The metal plate is contacted with the conductive pattern(42) for the ground of substrate and earth the electromagnetic wave generated from the first semiconductor chip(34) which is the radio frequency chip. The second semiconductor chip(36) which is the base band chip is adhered on the metal plate. A wire(22) connects a conductive pattern(18) for the wire bonding and a bonding pad of the second semiconductor chip. A plurality of trenches(46) connected with the cavity are concavely formed.
摘要翻译：提供半导体封装以提高封装中的系统的稳定叠层结构以及电磁干扰屏蔽和封装尺寸减小结构。在衬底（20）的芯片粘合区域中形成空腔。无源器件（14）安装在芯片粘附区域的外部位置。空腔被用于电磁干扰屏蔽的金属板（32）覆盖。金属板与用于基板接地的导电图案（42）接触，并将由作为射频芯片的第一半导体芯片（34）产生的电磁波接地。作为基带芯片的第二半导体芯片（36）粘附在金属板上。线（22）连接用于引线接合的导电图案（18）和第二半导体芯片的接合焊盘。与空腔连接的多个沟槽（46）被凹入地形成。

6. 发明公开

KR1020090017248A 반도체 패키지 및 그 제조 방법 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：KR1020090017248A
公开(公告)日：2009-02-18
申请号：KR1020070081849
申请日：2007-08-14
申请人： 앰코 테크놀로지 코리아 주식회사
发明人： 이창덕 , 이민재 , 정부양 , 이동희 , 전익수 , 박동주 , 강대병 , 김진성
IPC分类号： H01L23/12
CPC分类号： H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/73204 , H01L2224/73257 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor package and manufacturing method thereof are provided to omit the additional lamination process by stacking the semiconductor die using bond pads. The first silicon wafer(100) has the third side(100c) connecting the flat second side(100b), the flat first side(100a). The first active layer(220) has the first side and the second side, and is formed in the first side of the first silicon wafer. A plurality of first bond pads(240) is formed in the first side of the first active layer in order to be electrically connected to the first active layer. The first passivation layer(260) is formed in the first side of the first active layer and exposes the first bond pad. The second active layer(320) is formed in the second side of the first silicon wafer. The second semiconductor die(300) comprises the second passivation layer(360) exposing the second bond pad. The first penetration electrode(400) electrically connects the first semiconductor die(200) and the second semiconductor die. The first solder bump (500) is electrically connected with the second bond pad.
摘要翻译：提供半导体封装及其制造方法，以通过使用接合焊盘堆叠半导体管芯来省略附加层压工艺。第一硅晶片（100）具有连接扁平的第二侧（100b），平坦的第一侧（100a）的第三侧（100c）。第一有源层（220）具有第一侧和第二侧，并且形成在第一硅晶片的第一侧。多个第一接合焊盘（240）形成在第一有源层的第一侧中以便电连接到第一有源层。第一钝化层（260）形成在第一有源层的第一侧并且暴露第一接合焊盘。第二有源层（320）形成在第一硅晶片的第二侧。第二半导体管芯（300）包括暴露第二接合焊盘的第二钝化层（360）。第一穿透电极（400）电连接第一半导体管芯（200）和第二半导体管芯。第一焊料凸块（500）与第二接合焊盘电连接。

7. 发明授权

KR100370844B1 반도체패키지제조를위한마킹방법 有权
公开(公告)号：KR100370844B1
公开(公告)日：2003-07-07
申请号：KR1019980035620
申请日：1998-08-31
申请人： 앰코 테크놀로지 코리아 주식회사
发明人： 윤주훈 , 강대병 , 박인배
IPC分类号： H01L23/544
CPC分类号： H01L2924/014
摘要： PURPOSE: A marking method for fabricating semiconductor package is provide to reduce the number of manufacturing process and enhance productivity. CONSTITUTION: The marking method for fabricating semiconductor package comprises: a step presenting a wafer; a step presenting a circuit tape; a step bonding said wafer and circuit tape; a wire bonding step connecting said wafer and circuit tape by a wire; an encapsulation step coating said wire bonding portion with sealing material and curing it; a solder ball bumping step bumping a solder ball; a step cutting plural semiconductor chips along a street line on said wafer to form a semiconductor package having the same size as that of the chip; and a step picking up said cut semiconductor package, dividing good package and rework package through inspection, marking said packages with rotation state by 180 degree, and separating the good and rework packages.
摘要翻译：目的：提供一种制造半导体封装的标记方法，以减少制造工艺的数量并提高生产率。构成：用于制造半导体封装的标记方法包括：呈现晶片的步骤; 呈现电路磁带的步骤; 台阶结合所述晶片和电路带; 通过导线连接所述晶片和电路带的导线键合步骤; 密封步骤，用密封材料涂覆所述引线键合部分并固化它; 焊球碰撞步骤，碰撞焊球; 沿着所述晶片上的街道线切割多个半导体芯片以形成具有与所述芯片相同尺寸的半导体封装的步骤; 以及拾取所述切割的半导体封装的步骤，通过检查分割好的封装和返工封装，将所述封装旋转180度标记，并分离好的封装和返工封装。

8. 发明公开

KR1020000015589A 반도체패키지용 써킷테이프 有权
标题翻译：半导体封装用电路带
公开(公告)号：KR1020000015589A
公开(公告)日：2000-03-15
申请号：KR1019980035615
申请日：1998-08-31
申请人： 앰코 테크놀로지 코리아 주식회사
发明人： 윤주훈 , 강대병
IPC分类号： H01L23/48
CPC分类号： H01L2924/014
摘要： PURPOSE: A circuit tape for semiconductor package is provided to prevent a bowing phenomenon of the circuit tape. CONSTITUTION: A circuit tape for semiconductor package comprises: a polyimide layer(2) which is an insulator and has nearly flat shape; circuit pattern regions(4) where a number of units are integrated in a center part of the polyimide layer(2) and has a nearly wafer shape; conductive thin films(14) formed at circumference of the circuit pattern regions(4) on the polyimide layer(2) with a predetermined space and having a bowing preventing parts(16) formed of polyimide layer at a part of the circuit pattern regions(4); a number of tie bars(18) extended from the circumference of the circuit pattern regions(4) on the polyimide layer(2) to the conductive thin films(14); and a cover coat(12) coated on the circuit pattern regions(4), conductive thin films(14) and tie bars(18), thereby preventing an overall bowing phenomenon of the circuit tape by the bowing preventing part.
摘要翻译：目的：提供用于半导体封装的电路带以防止电路带的弯曲现象。构成：用于半导体封装的电路胶带包括：绝缘体并具有接近平坦形状的聚酰亚胺层（2）电路图形区域（4），其中多个单元集成在聚酰亚胺层（2）的中心部分并具有接近晶片形状; 导电薄膜（14），其形成在聚酰亚胺层（2）上的电路图案区域（4）的周围，具有预定空间，并且在电路图案区域的一部分具有由聚酰亚胺层形成的弯曲防止部分（16） 4）; 多个从聚酰亚胺层（2）上的电路图形区域（4）的圆周延伸到导电薄膜（14）的拉杆（18）; 以及涂覆在电路图案区域（4），导电薄膜（14）和连接条（18）上的覆盖层（12），从而防止由弯曲阻止部分引起的电路带的整体弯曲现象。

9. 发明公开

KR1020000015587A 반도체패키지의 제조에 적용되는 써킷테이프 有权
标题翻译：用于制作半导体封装的电路胶带
公开(公告)号：KR1020000015587A
公开(公告)日：2000-03-15
申请号：KR1019980035613
申请日：1998-08-31
申请人： 앰코 테크놀로지 코리아 주식회사
发明人： 윤주훈 , 강대병
IPC分类号： H01L23/48
CPC分类号： H01L2924/014
摘要： PURPOSE: A circuit tape is provided to easily identify a cutting line of a wafer in a state that the circuit tape is adhered on the wafer. CONSTITUTION: A circuit tape comprises: a polyimide layer(2) which is an insulator and has nearly flat shape; a circuit pattern region(4) having bond fingers(5a) formed on the polyimide layer(2) and to be wire bonded with input and output pads(20) of the semiconductor chip of the wafer, circuit patterns(5) connected to the bond fingers(5a), and grooves(8) for identifying cutting line(22) formed on the cutting line for easily identifying a cutting line of the wafer, wherein solder ball lands(6) are formed at the circuit pattern; and a cover coat(12) coated on the circuit pattern region for protect a circuit pattern region except the grooves(8) for identifying the cutting line, solder ball lands(6) and bond finger regions(5b) from external environment.
摘要翻译：目的：提供一种电路胶带，用于在电路胶带粘附在晶片上的状态下容易地识别晶片的切割线。构成：电路胶带包括：聚酰亚胺层（2），其是绝缘体并具有接近平坦的形状; 具有形成在聚酰亚胺层（2）上并且与晶片的半导体芯片的输入和输出焊盘（20）引线接合的接合指状物（5a）的电路图案区域（4），连接到晶片的电路图案（5）用于识别形成在切割线上的切割线（22）的凹槽（8），用于容易地识别晶片的切割线，其中以电路图案形成焊球接地（6）; 以及涂覆在电路图案区域上的覆盖层（12），用于保护除了用于识别切割线的凹槽（8）之外的电路图案区域，防止外部环境中的焊球焊盘（6）和粘结指状区域（5b）。

10. 发明授权

KR101647548B1 싱귤레이티드 유닛 서브스트레이트를 이용한 반도체 디바이스 및 그 제조 방법 有权
标题翻译：使用单位衬底的半导体器件及其制造方法
公开(公告)号：KR101647548B1
公开(公告)日：2016-08-10
申请号：KR1020140051887
申请日：2014-04-29
申请人： 앰코 테크놀로지 코리아 주식회사
发明人： 김근수 , 안병준 , 이춘흥 , 김진영 , 강대병 , 세인트아만드로저
IPC分类号： H01L21/78 , H01L21/301
CPC分类号： H01L21/78 , H01L21/56 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/95 , H01L2224/131 , H01L2224/13147 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/83005 , H01L2224/83104 , H01L2224/92125 , H01L2224/95 , H01L2224/95001 , H01L2924/15311 , H01L2224/81 , H01L2224/83 , H01L2924/00014 , H01L2924/014
摘要： 본발명의일 실시예는반도체디바이스및 그제조방법에관한것으로, 해결하고하고자하는기술적과제는양품의싱귤레이티드유닛서브스트레이트만을이용하여반도체디바이스를제조함으로써제조수율을향상시키는데있다. 이를위해본 발명은상면및 하면에형성된회로패턴을포함하는싱귤레이티드유닛서브스트레이트; 상기싱귤레이티드유닛서브스트레이트의상면에접속된반도체다이; 및, 상기반도체다이를인캡슐레이션하고, 상기싱귤레이티드유닛서브스트레이트의상면을덮는인캡슐란트를포함하고, 상기싱귤레이티드유닛서브스트레이트의상면및 하면사이의상기싱귤레이티드유닛서브스트레이트의측면이상기인캡슐란트의측면과동일한평면이되도록절단된반도체디바이스및 그제조방법을개시한다.

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