基本信息:
- 专利标题： 메모리 시스템 및 메모리 인터페이스 장치
- 专利标题（英）：Memory system and memory interface device
- 专利标题（中）：存储器系统和存储器接口设备
- 申请号：KR1020127030883 申请日：2010-05-27
- 公开(公告)号：KR101426187B1 公开(公告)日：2014-07-31
- 发明人： 기타고게이타 , 오와키다케시 , 이시즈카다카하루 , 가와노히로시 , 모로사와아츠시
- 申请人： 후지쯔 가부시끼가이샤
- 申请人地址： 일본국 가나가와켄 가와사키시 나카하라꾸 가미고다나카 *초메 *-*
- 专利权人： 후지쯔 가부시끼가이샤
- 当前专利权人： 후지쯔 가부시끼가이샤
- 当前专利权人地址： 일본국 가나가와켄 가와사키시 나카하라꾸 가미고다나카 *초메 *-*
- 代理人： 송승필
- 国际申请： PCT/JP2010/058972 2010-05-27
- 国际公布： WO2011148483 2011-12-01
- 主分类号： G11C7/10
- IPC分类号： G11C7/10 ; G06F12/02
Memory access source (3), access to regard the plurality of memory circuits (DIMM0,1) as a memory circuit, and transmits the row address and column address in a time sharing manner, and specifying one of the plurality of memory circuits to the column address a control circuit 20, when receiving the row address and then subjected to a dumping access to a plurality of memory circuits, receives the column address, speculative access the performed access only to the particular memory circuit, the excluded access memory circuit of It sends a command of the cleanup. Or, in the case of a read access, it receives the data read out of a particular memory circuit, and discards the read data of the memory circuit of the excluded access. Therefore, it is possible to reduce the latency (Latency) of the memory access.
公开/授权文献:
- KR1020130028110A 메모리 시스템 및 메모리 인터페이스 장치 公开/授权日：2013-03-18
信息查询:
EspacenetIPC结构图谱:
| G | 物理 |
| --G11 | 信息存储 |
| ----G11C | 静态存储器 |
| ------G11C7/00 | 数字存储器信息的写入或读出装置 |
| --------G11C7/10 | .输入/输出（I/O）数据接口装置，例如，I/O数据控制电路，I/O数据缓冲器 |