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1. 发明申请

WO1997032415A1 HIGH SPEED DATA COMMUNICATIONS USING MULTIPLE LOW SPEED MODEMS 审中-公开
标题翻译：使用多种低速模式的高速数据通信
公开(公告)号：WO1997032415A1
公开(公告)日：1997-09-04
申请号：PCT/US1997002860
申请日：1997-02-26
申请人： ENCANTO NETWORK, INC.
发明人： ENCANTO NETWORK, INC. , KRISHAN, Kalyan, V. , SALINAS, Leo
IPC分类号： H04L05/16
CPC分类号： H04L25/14
摘要： Method and apparatus for providing high speed inter-computer data transmission is achieved by using multiple low speed communication links connected in parallel (16, 18). At the transmitting site, a high speed data stream received from a source (10) is split into multiple low speed data streams and multiplexed onto the low speed links (16, 18). The receiver demultiplexes, buffers, and synchronizes the multiple low speed data streams to recreate the high speed data stream.
摘要翻译：通过使用并联连接的多个低速通信链路（16,18）来实现提供高速计算机间数据传输的方法和装置。在发送站点，从源（10）接收的高速数据流被分割成多个低速数据流并被复用到低速链路（16,18）上。接收机对多个低速数据流进行解复用，缓冲和同步，以重新创建高速数据流。

2. 发明申请

WO1997042730A1 HALF DUPLEX UART CONTROL FOR SINGLE CHANNEL BI-DIRECTIONAL WIRELESS COMMUNICATIONS 审中-公开
标题翻译：用于单通道双向无线通信的半双工UART控制
公开(公告)号：WO1997042730A1
公开(公告)日：1997-11-13
申请号：PCT/US1997007665
申请日：1997-05-06
申请人： ERICSSON INC.
发明人： ERICSSON INC. , MOON, Billy, G.
IPC分类号： H04L05/16
CPC分类号： H04L5/18 , H04L5/16
摘要： A UART including a logic unit is disclosed, wherein the logic unit automatically enables or disables the UART receiver port whenever data is being processed by the UART for wireless transmission. More specifically, a logic unit is connected to a data store, to a transmit FIFO and to a UART processing unit as well as to an external CPU, wherein the logic unit analyzes the logic states of each of the signals from each of the specified connections to determine whether to enable or disable the receiver unit. An inventive method is also disclosed wherein the logic unit only enables the receiver when the data store is empty and the transmitter FIFO is empty and a receiver enable flag is set to true and a half duplex mode of operation has been specified by an external CPU. Otherwise, the logic enables the receiver only when a full duplex mode of operation has been specified and the receiver enable flag is set to a logic one.
摘要翻译：公开了一种包括逻辑单元的UART，其中当UART进行无线传输的数据处理时，逻辑单元自动启用或禁用UART接收器端口。更具体地，逻辑单元连接到数据存储器，连接到发送FIFO和UART处理单元以及外部CPU，其中逻辑单元分析来自每个指定连接的每个信号的逻辑状态以确定是否启用或禁用接收器单元。还公开了一种创新的方法，其中当数据存储器为空并且发送器FIFO为空并且接收器使能标志被设置为真并且外部CPU已经指定了半双工操作模式时，逻辑单元仅允许接收器。否则，仅当指定了全双工工作模式并且接收器使能标志被设置为逻辑1时，逻辑才能使能接收器。

3. 发明申请

WO1993016537A1 HIGH SPEED MODEM SYSTEMS INCORPORATING DISTRIBUTION PRESERVING TOMLINSON ENCODING AND DECODING FOR SECONDARY CHANNELS 审中-公开
标题翻译：高速调制解调器系统进行分配保存TOMLINSON编码和解码二次通道
公开(公告)号：WO1993016537A1
公开(公告)日：1993-08-19
申请号：PCT/US1993001099
申请日：1993-02-08
申请人： GENERAL DATACOMM, INC.
发明人： GENERAL DATACOMM, INC. , GOLDSTEIN, Yuri , COLE, Paul, Dana
IPC分类号： H04L05/16
CPC分类号： H03M13/25 , H03M13/256 , H04L25/03343 , H04L25/49 , H04L25/4975 , H04L27/34 , H04L27/3461 , H04L2025/03802
摘要： Apparatus and methods in both modem transmitters (50) and receivers (130) are provided for accommodating secondary channel data without disturbing the trellis encoding, mapping, and Viterbi decoding of primary channel data, and without disturbing distribution preserving Tomlinson precoding and decoding of the primary channel data. In order to accommodate the secondary channel data, the secondary channel data are used to make quadrant decisions in a mapper (60), and concurrently therewith, dummy data or tertiary channel data corresponding in time with the secondary channel data are provided to the trellis encoder (55) so that the continuous working of the trellis encoder (55) can be maintained. In order to guarantee proper working of the trellis encoder (55), the secondary channel constellation points within a quadrant are clustered together and far from the quadrant boundaries.
摘要翻译：提供调制解调器发射机（50）和接收机（130）中的装置和方法用于容纳辅助信道数据，而不会干扰主信道数据的网格编码，映射和维特比解码，并且不干扰分配，保持对主要信道的Tomlinson预编码和解码频道数据为了适应辅助信道数据，二次信道数据被用于在映射器（60）中进行象限判定，并且与此同时，与辅助信道数据对应的伪数据或三次信道数据被提供给网格编码器（55），从而可以保持网格编码器（55）的连续工作。为了保证网格编码器（55）的正常工作，象限内的二次通道星座点聚集在一起，远离象限边界。

4. 发明申请

WO1995009497A1 METHOD FOR DIGITAL SEMI-DUPLEX TRANSMISSION 审中-公开
标题翻译：数字半双工传输方法
公开(公告)号：WO1995009497A1
公开(公告)日：1995-04-06
申请号：PCT/FI1994000431
申请日：1994-09-26
申请人： NOKIA TELECOMMUNICATIONS OY , MÄKELÄINEN, Kimmo , LEHMUSTO, Mika , HEISKARI, Mika
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H04L05/16
CPC分类号： H04J3/12 , H04J3/06
摘要： A method for digital semi-duplex transmission. To allow transmission of information to subscribers during the transmitting permission of one of the subscribers, a selected number (N-1) of blocks are transmitted during a time period shorter than the original total duration (t) of the blocks from a subscriber (MS A) having the permission to transmit to a base station (BS) having the permission to receive; the base station (BS) having the receiving permission utilizes the original total duration (t) of the blocks reduced by the actual transmission period of the blocks and by a first and a second guard period (301, 302) for transmitting reverse information (203) and time synchronization information (202) to the subscriber having the transmitting permission; and the base station (BS) having the receiving permission transmits information during at least one of said guard periods (301, 302) to at least one subscriber (MS B) having no transmitting permission.
摘要翻译：一种数字半双工传输的方法。为了在一个用户的发送许可期间允许向用户发送信息，在比来自用户（MS）的块的原始总持续时间（t）短的时间段内发送所选择的数量（N-1）个块 A）具有允许发送到具有接收许可的基站（BS）的许可; 具有接收许可的基站（BS）利用减少了块的实际传输周期的块的原始总持续时间（t）和用于发送反向信息的第一和第二保护周期（301,302））和具有发送许可的用户的时间同步信息（202）; 并且具有接收许可的基站（BS）在至少一个所述保护周期（301,302）内向至少一个没有发送许可的用户（MS B）发送信息。

5. 发明申请

WO1990004296A1 AN INTERFACE FOR USE BETWEEN TWO COMMUNICATION UNITS 审中-公开
标题翻译：两个通信单元之间的接口
公开(公告)号：WO1990004296A1
公开(公告)日：1990-04-19
申请号：PCT/EP1988000904
申请日：1988-10-10
申请人： ROBERT BOSCH GMBH , RIEHEMANN, Thomas
发明人： ROBERT BOSCH GMBH
IPC分类号： H04L05/16
CPC分类号： H04L5/16
摘要： An interface for use between a first communication unit having a two-wire connection and a second communication unit having a single-wire connection includes a comparator (IC1) having a fixed potential (V(-)) at its inverting input and has its output connected to one of the two-wire connections whilst the potential (V(+)) applied to the non-inverting input is determined by a switching network (transistors T1 and T2 and resistors R2, R3, R4, R7, R12) responsive to the potential on the second of the two-wire connections and on the single-wire connection to enable the first communication unit to receive data from the second communication unit but not receive self-transmitted data.
摘要翻译：在具有双线连接的第一通信单元和具有单线连接的第二通信单元之间使用的接口包括在其反相输入端具有固定电位（V（ - ））的比较器（IC1），并具有其输出连接到两线连接中的一个，而施加到非反相输入的电位（V（+））由开关网络（晶体管T1和T2以及电阻器R2，R3，R4，R7，R12）决定，响应于两线连接的第二个和单线连接上的电位使第一通信单元能够从第二通信单元接收数据，但不接收自发数据。

6. 发明申请

WO1997009801A1 AUDIO FILE DISTRIBUTION AND PRODUCTION SYSTEM 审中-公开
标题翻译：音频文件分发和制作系统
公开(公告)号：WO1997009801A1
公开(公告)日：1997-03-13
申请号：PCT/US1996013898
申请日：1996-08-30
申请人： STARGUIDE DIGITAL NETWORKS, INC. , CHASE, Tim
发明人： STARGUIDE DIGITAL NETWORKS, INC.
IPC分类号： H04L05/16
CPC分类号： H04H20/103 , H04H20/40 , H04H20/42 , H04H20/74 , H04H60/06 , H04H60/07 , H04H60/13 , H04H2201/70
摘要： A data file delivery system (10) is provided having, at a head end, a production subsystem (12) which communicates with a delivery subsystem (14) via a local area network, ISDN connection, and the like. The delivery subsystem (14) communicates with an affiliate subsystem (16), at a tail end, via a satellite link, ISDN link and the like. The production subsystem (12) enable a producer to create audio which are played to completion before another audio event occurs. Audio events are stored as audio files. Each audio event may include one or more of an audio sequence, test information, delivery instructions, and an attribute list having contact closure information and the like. Optionally, multiple audio events may be assembled at the production subsystem (12) to form a play list. The audio files are transferred to the delivery subsystem (14). The delivery subsystem (14) places the audio files in delivery envelopes and transmits the envelopes to the affiliate terminals. In addition, the delivery subsystem (14) may transmit live audio and related contact closure information to the affiliate terminals (16). The affiliate terminal (16) may be located at the user site. The affiliate terminals (16) may store these events on the hard drive, play the events in real time or pass events to other affiliate terminals (16). The affiliate terminal (16) may later play stored audio events.
摘要翻译：提供了一种数据文件传送系统（10），其在头端具有经由局域网，ISDN连接等与传送子系统（14）进行通信的生产子系统（12）。传送子系统（14）通过卫星链路，ISDN链路等在尾端与分支子系统（16）进行通信。生产子系统（12）使生产者创建在另一音频事件发生之前播放完成的音频。音频事件存储为音频文件。每个音频事件可以包括音频序列，测试信息，传送指令和具有接触闭合信息等的属性列表中的一个或多个。可选地，可以在生产子系统（12）处组装多个音频事件以形成播放列表。音频文件被传送到传送子系统（14）。传送子系统（14）将音频文件放置在传送信封中，并将信封发送给会员终端。另外，传送子系统（14）可以向联属终端（16）发送现场音频和相关的联系人关闭信息。会员终端（16）可以位于用户站点。附属终端（16）可以将这些事件存储在硬盘驱动器上，实时播放事件或将事件传递到其他联属终端（16）。会员终端（16）可以稍后播放存储的音频事件。

7. 发明申请

WO1996037983A1 VIDEO PEDESTAL NETWORK 审中-公开
标题翻译：视频网络
公开(公告)号：WO1996037983A1
公开(公告)日：1996-11-28
申请号：PCT/US1996007105
申请日：1996-05-16
申请人： HYUNDAI ELECTRONICS AMERICA, INC. , RAO, R., Padmanabha , SICCARDO, Paolo, L. , LEVESQUE, Gilbert
发明人： HYUNDAI ELECTRONICS AMERICA, INC.
IPC分类号： H04L05/16
CPC分类号： H04N7/17336 , H04H20/38 , H04H20/81 , H04H60/94 , H04L12/2801 , H04L12/2856 , H04L12/2883 , H04L12/4633 , H04L47/2408 , H04M11/062 , H04N7/108 , H04N7/148 , H04N7/173 , H04N7/17354 , H04N21/222 , H04N21/2362 , H04N21/2365 , H04N21/4347 , H04N21/47202 , H04N21/47208 , H04N21/6125 , H04N21/6137 , H04N21/6377 , H04N21/64307 , H04N21/64784 , H04N21/658 , H04N21/6581 , H04N21/6587
摘要： An architecture (200) for distributing digital information to subscriber units (202) wherein selection from among multiple digital services is accomplished by transmitting a tuning command from a subscriber unit to an intermediate interface (206). The intermediate interface (206) selects the desired service from a broadband network and transmits it to the subscriber unit (202) over a bandwidth-constrained access line. The bandwidth-constrained access line may be implemented with existing infrastructure, yet the subscriber unit (202) may access a wide variety of digital information available on the broadband network. Universal broadband access is thus provided at low cost. Output bandwidth of broadcast equipment may also be optimized.
摘要翻译：一种用于向用户单元（202）分发数字信息的架构（200），其中通过从用户单元向中间接口（206）发送调谐命令来实现多个数字服务之间的选择。中间接口（206）从宽带网络中选择所需的服务，并通过带宽限制的接入线路将其发送到用户单元（202）。带宽有限的接入线路可以用现有的基础设施来实现，而用户单元（202）可以访问宽带网络上可用的各种数字信息。因此以低成本提供通用宽带接入。广播设备的输出带宽也可以优化。

8. 发明申请

WO1996005671A1 BIDIRECTIONAL BUFFER 审中-公开
标题翻译：双向缓冲
公开(公告)号：WO1996005671A1
公开(公告)日：1996-02-22
申请号：PCT/EP1995003178
申请日：1995-08-10
申请人： ICL SYSTEMS AB , THÖRNBLAD, Hans
发明人： ICL SYSTEMS AB
IPC分类号： H04L05/16
CPC分类号： H04L25/028 , H03K19/01759 , H03K19/1732 , H04L5/16 , H04L25/0292
摘要： A buffer circuit for use between a two-way open-collector bus line (4) and a device (D) capable of reading the status of the bus line and driving it low. The device has a single input/output terminal (1) to which is connected a line (7) of the buffer circuit. The buffer circuit is such as to distinguish between three logical levels on the line, and in particular between two logical low levels (Ua, Ub), which correspond to the device (1) or the input buffer (C1) driving the bus line low. The input and output buffers are comprised by respective comparators (C1, C2). The reference voltage for the output buffer comparator lies between Ua and Ub, whereby to achieve the distinction therebetween. When the output buffer comparator detects Ua, it causes the bus line (4) to be driven low.
摘要翻译：一种用于双向开路集电极总线（4）和能够读取总线状态并将其驱动的装置（D）的缓冲电路。该装置具有单个输入/输出端子（1），其连接到缓冲电路的线路（7）。缓冲电路是为了区分线路上的三个逻辑电平，特别是对应于驱动总线低电平的设备（1）或输入缓冲器（C1）的两个逻辑低电平（Ua，Ub）之间。。输入和输出缓冲器由相应的比较器（C1，C2）组成。输出缓冲器比较器的参考电压位于Ua和Ub之间，从而实现它们之间的区别。当输出缓冲器比较器检测到Ua时，它使总线（4）被驱动为低电平。

9. 发明申请

WO1994013078A1 CIRCUIT ARRANGEMENT FOR CONTROLLING A PLURALITY OF USERS, ESPECIALLY LAMP BALLASTS 审中-公开
标题翻译：电路，用于控制消费者的数字，尤其是镇流器灯具
公开(公告)号：WO1994013078A1
公开(公告)日：1994-06-09
申请号：PCT/EP1993003166
申请日：1993-11-11
申请人： TRIDONIC BAUELEMENTE GMBH , LUGER, Siegfried , WERNER, Walter
发明人： TRIDONIC BAUELEMENTE GMBH
IPC分类号： H04L05/16
CPC分类号： H02J13/0062 , H02J13/0079 , H05B37/0254 , Y02B70/3283 , Y02B90/2638 , Y04S20/246 , Y04S40/124 , Y10T307/25 , Y10T307/461 , Y10T307/469
摘要： The circuit arrangement of the invention consists of a central unit (5) and a plurality of peripheral units, e.g. control devices for lamps, connected thereto via a databus. The lamps are connected to the databus (1) via a coupling unit (3), each coupling unit (3) having a reception branche for the transfer of information from the central unit (5) to the peripheral unit and a transmission branche for the transfer of information from the peripheral unit to the central unit (5). The central unit (5) provides the databus with information in the form of a modulated alternating or pulsed voltage. The transmission branch provides the databus (1) with information by varying the output resistance of the transmission branch. As the reception branch in the coupling unit (3) is always active and the transmission branch is inactive when no transmission are being made, only a very low reverse current is used in the coupling unit (3). Finally, on overvoltage protective circuit is fitted for both the reception and the transmission branch.

10. 发明申请

WO1997023970A1 INTERPOLATION SYSTEM FOR FIXED SAMPLE RATE SIGNAL PROCESSING 审中-公开
标题翻译：固定速率信号处理的插值系统
公开(公告)号：WO1997023970A1
公开(公告)日：1997-07-03
申请号：PCT/US1996020325
申请日：1996-12-20
申请人： PARADYNE CORPORATION
发明人： PARADYNE CORPORATION , BETTS, William, Lewis , SOUDERS, Keith, Alan
IPC分类号： H04L05/16
CPC分类号： H03H17/0657 , H03H17/0664 , H04L5/16 , H04L25/05
摘要： Using digital signal processing in a modem attached to a digital line, the modem sample rate for both transmit and receive signals is interpolated or decimated to the time slot rate of a digital channel connected to the modem by filters (101) which are operated by a unified interpolation/decimation filter controller (111) as a function of a modulo counter (113). A modem signal is developed as if it were to be supplied to a codec. However, instead of being supplied to the codec, the signal is filtered using low pass finite impulse response digital filter (101). The resulting filtered signal is sampled at the time slot rate and supplied in companded form as an output to the time slots of the digital line. Prior to operating the filter (101), the ratio of the time slot rate to the sample rate is determined. The ratio is expressed in a form that is a ratio of the smallest possible integers. The numerator of the resulting ratio is designated P and the denominator is designated I. The coordination between the development of the modem signal sample and the filter operation is under the control of a modulo counter (113) that has a modulus of P.
摘要翻译：在连接到数字线路的调制解调器中使用数字信号处理，将发送和接收信号的调制解调器采样率内插或抽取到通过滤波器（101）连接到调制解调器的数字信道的时隙率，作为模计数器（113）的函数的统一内插/抽取滤波器控制器（111）。开发调制解调器信号，就像将其提供给编解码器一样。然而，不是提供给编解码器，而是使用低通有限脉冲响应数字滤波器（101）对信号进行滤波。所得到的滤波信号以时隙率采样，并以压缩形式作为输出提供给数字线的时隙。在操作过滤器（101）之前，确定时隙率与采样率的比率。该比率以最小可能整数的比率的形式表示。所得到的比率的分子被指定为P，分母被指定为I.调制解调器信号样本的发展与滤波器操作之间的协调是在具有模数P.的模计数器（113）的控制下。

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