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1. 发明申请

WO2020257531A1 MIXED-SIGNAL ACCELERATION OF DEEP NEURAL NETWORKS 审中-公开
公开(公告)号：WO2020257531A1
公开(公告)日：2020-12-24
申请号：PCT/US2020/038551
申请日：2020-06-18
申请人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
发明人： GHODRATI, Soroush , ESMAEILZADEH, Hadi
IPC分类号： H03M1/12 , H03M1/14 , H03M1/18 , H03M1/72
摘要： Disclosed are devices, systems and methods for accelerating vector-based computation. In one example aspect, an accelerator apparatus includes a plurality of mixed-signal units, each of which includes a first digital-to-analog convertor configured to convert a subset of digital-domain bits to a first analog-domain signal and a second digital-to-analog convertor configured to convert a subset of digital-domain bits to a second analog-domain signal. Each mixed-signal unit also includes a capacitor coupled to the digital-to-analog convertors to accumulate a result of a multiplication operation as an analog signal. The apparatus includes a circuitry coupled to the mixed-signal units to shift part of the analog signals of the plurality of mixed-signal units. The circuitry comprises an additional capacitor to store an analog-domain result for a multiply-accumulate operation. The apparatus also includes an analog-to-digital converter coupled to the circuitry to convert the analog-domain result into a digital-domain result.

2. 发明申请

WO99044289A1 DIGITAL TO ANALOGUE CONVERTER WITH DYNAMIC ELEMENT MATCHING 审中-公开
标题翻译：数字转换器与动态元件匹配
公开(公告)号：WO99044289A1
公开(公告)日：1999-09-02
申请号：PCT/GB1999/000472
申请日：1999-02-16
IPC分类号： H03M1/06 , H03M1/72 , H03M3/04
CPC分类号： H03M1/0668 , H03M1/0641 , H03M1/72 , H03M3/464 , H03M3/502
摘要： A digital to analogue converter (DAC) system (30) is described which has a plurality of weighting elements (40) where some of the weighting elements have a different nominal weight from other elements. In a preferred arrangement pairs of elements with the same nominal weight are combined, with each pair of elements having more than two output states. A selection unit is coupled to the elements and an adder is coupled to the selection unit to sum the outputs of the weighted elements. In use, the DAC system receives a digital signal and the selection unit determines the output state of each element combination to provide values of the weighted elements which, when summed, are equivalent to the digital signal. The selection unit also determines the output state of each element in each element combination to minimise errors. An analogue to digital (A/D) converter (200) based on the DAC is also described.
摘要翻译：描述了一种数模转换器（DAC）系统（30），其具有多个加权元件（40），其中一些加权元件具有与其它元件不同的标称重量。在优选布置中，组合具有相同标称重量的元件对，其中每对元件具有多于两个的输出状态。选择单元耦合到元件，并且加法器耦合到选择单元以对加权元件的输出求和。在使用中，DAC系统接收数字信号，并且选择单元确定每个元件组合的输出状态，以提供加权元素的值，其在相加时等于数字信号。选择单元还确定每个元素组合中的每个元素的输出状态以最小化错误。还描述了基于DAC的模数（A / D）转换器（200）。

3. 发明申请

WO0141310A9 DIGITAL-TO-ANALOG CONVERTER 审中-公开
标题翻译：数字到模拟转换器
公开(公告)号：WO0141310A9
公开(公告)日：2002-10-03
申请号：PCT/JP0008248
申请日：2000-11-22
申请人： YAMAHA CORP , NORO MASAO , TODA AKIHIKO
发明人： NORO MASAO , TODA AKIHIKO
IPC分类号： H03M1/68 , H03M1/06 , H03M1/72 , H03M1/74 , H03M1/76
CPC分类号： H03M1/0619 , H03M1/687 , H03M1/745 , H03M1/765
摘要： A decoder (21) selects one of FETs (F0 to F255) based on higher bits, and applies one of the voltages divided by a series circuit of resistors (r0 to r255) to an operational amplifier (40). Switches (30 to 33) of a current adder circuit (22) are switched by lower bits to turn on and off FETs (35 to 38). The currents flowing through the conducting FETs are combined, and the resulting current flows to a resistor (ra), across which a voltage appears. The operational amplifier (40) combines two input voltages to produce an output. A FET (24) and FETs (35 to 38) form a current mirror circuit, which prevents the voltage width of each LSB of higher and lower bits from changing if the current (i) through the series circuit of resistors (r0 to r255) changes because of irregularities of manufacturing processes.
摘要翻译：解码器（21）基于较高位选择FET（F0〜F255）中的一个，并且将由电阻（r0〜r255）的串联电路分压的电压中的一个施加到运算放大器（40）。电流加法器电路（22）的开关（30〜33）由低位开关导通和截止FET（35〜38）。流过导通FET的电流被组合，并且所得到的电流流向电阻（ra），电阻出现在电阻（ra）上。运算放大器（40）组合两个输入电压以产生输出。 FET（24）和FET（35〜38）形成电流镜电路，如果电流（i）通过电阻（r0〜r255）的串联电路，则阻止高位和低位的每个LSB的电压宽度改变，由于制造过程的不规则而改变。

4. 发明申请

WO01013522A1 CURVE SELECTION DIGITAL-TO-ANALOG CONVERTER CIRCUIT 审中-公开
标题翻译：曲线选择数字到模拟转换器电路
公开(公告)号：WO01013522A1
公开(公告)日：2001-02-22
申请号：PCT/US2000/021815
申请日：2000-08-10
IPC分类号： H03M1/72 , H03M1/66
CPC分类号： H03M1/72
摘要： In a unit DAC (100), curve selection signal is done by different bias voltages or different amplifiers (D0, D1). One of the bits (104) is used as a MUX (104) switching signal. A number of units can be cascaded with each stage receiving a different bit of the digital signal.
摘要翻译：在单位DAC（100）中，曲线选择信号由不同的偏置电压或不同的放大器（D0，D1）完成。比特（104）中的一个被用作MUX（104）切换信号。多个单元可以级联，每个级接收数字信号的不同位。

5. 发明申请

WO99066642A1 DIGITAL-TO-ANALOG CONVERTER 审中-公开
标题翻译：数字到模拟转换器
公开(公告)号：WO99066642A1
公开(公告)日：1999-12-23
申请号：PCT/JP1999/003047
申请日：1999-06-08
IPC分类号： G06G7/186 , H03M1/06 , H03M1/08 , H03M1/66 , H03M1/72
CPC分类号： H03M1/661
摘要： A D/A converter for generating output waveforms with little distortion without the need for high-speed components. The D/A converter comprises a D/A converter (10), four voltage-holding sections (11-1 to 11-4), four step-function generators (12-1 to 12-4), a voltage summing section (14), two integrators (16, 18), and a timing control (20). The voltages corresponding to four sequential digital data inputs are held in the voltage holding sections, respectively, and the step-function generators generate step-function waveforms at the voltage levels corresponding to the held voltages. The voltage summing section (14) combines the step-function waveforms generated in the step-function generators, and two integrators (16, 18) integrate this combined waveform two times, thus producing a continuous analog voltage composed of the input digital data.
摘要翻译：一个D / A转换器，用于在不需要高速分量的情况下生成具有很小失真的输出波形。 D / A转换器包括D / A转换器（10），四个电压保持部分（11-1至11-4），四个步进函数发生器（12-1至12-4），电压求和部分 14），两个积分器（16,18）和定时控制（20）。对应于四个连续数字数据输入的电压分别保持在电压保持部分中，并且步进功能发生器产生与保持电压相对应的电压电平的阶梯函数波形。电压求和部分（14）组合在步进函数发生器中产生的阶梯函数波形，两个积分器（16,18）对该组合波形进行两次积分，从而产生由输入数字数据组成的连续模拟电压。

6. 发明申请

WO2006124168A1 DIGITAL AUTOMATIC GAIN CONTROL METHOD AND DEVICE 审中-公开
标题翻译：数字自动增益控制方法及装置
公开(公告)号：WO2006124168A1
公开(公告)日：2006-11-23
申请号：PCT/US2006/014275
申请日：2006-04-14
申请人： MOTOROLA, INC. , SAUNDERS, David R. , GLAESS, Jeffrey D. , HANSEN, Robert K. , HELWIG, Arthur P.
发明人： SAUNDERS, David R. , GLAESS, Jeffrey D. , HANSEN, Robert K. , HELWIG, Arthur P.
IPC分类号： H03M1/72
CPC分类号： H03M1/181
摘要： An automatic gain control device (110) includes a peak detector (202) configured to receive a current output of an ADC (108) and to compare it to a previous output to produce a peak value. The automatic gain control device (110) also includes an out-of-range indicator (204) configured to receive an out-of-range signal if an input to the ADC exceeds the dynamic range of the ADC. The out-of-range indicator (204) increases the peak value if the out-of-range indicator (204) receives the out-of range signal. An error detector (206) is coupled to the out-of-range indicator (204) and the peak detector (202) and produces an error level that is the difference of an output of the out-of-range indicator (204) and a pre-selected target value. The pre-selected target value is chosen to attenuate interference signals that exceed the dynamic range of the ADC (108) but minimizes the attenuation of communication signals.
摘要翻译：自动增益控制装置（110）包括峰值检测器（202），其被配置为接收ADC（108）的电流输出并将其与先前输出进行比较以产生峰值。自动增益控制装置（110）还包括超范围指示器（204），其被配置为如果ADC的输入超过ADC的动态范围，则接收超出范围的信号。超出范围指示符（204）如果超出范围指示符（204）接收到超出范围信号，则增加峰值。误差检测器（206）耦合到超出范围指示器（204）和峰值检测器（202），并产生误差电平，该误差电平是超出范围指示器（204）和预先选定的目标值。选择预选的目标值以衰减超过ADC（108）的动态范围的干扰信号，但是最小化通信信号的衰减。

7. 发明申请

WO02047274A1 DIFFERENTIAL BIPOLAR STRAY-INSENSITIVE PIPELINED DIGITAL-TO-ANALOG CONVERTER 审中-公开
标题翻译：差分双极型无源管道数字到模拟转换器
公开(公告)号：WO02047274A1
公开(公告)日：2002-06-13
申请号：PCT/US2001/046670
申请日：2001-12-04
IPC分类号： H03M1/06 , H03M1/72 , H03M1/38 , H03M1/12
CPC分类号： H03M1/06 , H03M1/72
摘要： A pipelined digital-to-analog converter "DAC" converts a digital input to an analog output. The pipelined DAC has a plurality of stages. A first of the plurality of stages is coupled to an initialization capacitor and ground. Each of the remainder of the plurality of stages is coupled to a respective previous stage. The capacitor (54) has first and second plates. The capacitor receives a charge at the first plate in accordance with an associated bit of the digital input. The first switch (56) coupled the first plate of the capacitor to ground when the capacitor is not receiving the charge. The second switch (58) couples the second plate of the capacitor to ground when the capacitor is receiving the charge. Coupling the capacitor to ground reduces the effect of stray capacitance in the pipelined DAC, improving its performance.
摘要翻译：流水线数模转换器“DAC”将数字输入转换为模拟输出。流水线式DAC具有多个级。多个级中的第一级耦合到初始化电容器和接地。多个级的其余部分中的每一个被耦合到相应的前一级。电容器（54）具有第一板和第二板。电容器根据数字输入的相关位在第一板处接收电荷。当电容器未接收电荷时，第一开关（56）将电容器的第一板耦合到地。当电容器接收电荷时，第二开关（58）将电容器的第二板耦合到地。将电容耦合到地降低了流水线DAC中杂散电容的影响，从而提高了其性能。

8. 发明申请

WO9827655A3 Pipeline analog-to-digital conversion 审中-公开
标题翻译：管道模拟 - 数字转换
公开(公告)号：WO9827655A3
公开(公告)日：1998-08-06
申请号：PCT/SE9702037
申请日：1997-12-05
申请人： ERICSSON TELEFON AB L M
发明人： SIGNELL SVANTE , JONSSON BENGT ERIK , STENSTROEM HELGE , TAN NIANXIONG
IPC分类号： H03M1/06 , H03M1/44 , H03M1/66 , H03M1/72
CPC分类号： H03M1/0687 , H03M1/0682 , H03M1/442 , H03M1/72
摘要： Pipeline A/D-conversion of an analog input signal is performed according to a new and inventive algorithm which generates a Gray coded digital output signal. A pipeline A/D-converter comprises a number of cascaded stages through which the analog input signal is propagated. Each stage generally generates an output bit of the digital output signal, and furthermore processes the pipeline signal. According to the inventive Gray coding algorithm, the output bit generated in a stage determines whether or not the pipeline signal of that stage is inverted. In a pipeling A/D-converter based on the Gray coding algorithm according to the invention, the accumulation of offset errors will generally be very low. Furthermore, the fact that the signal inversion is digitally controlled enables high precision implementations which further improve the performance of the inventive pipeline A/D-converter. In another embodiment of the invention, the Gray coding algorithm is modified to form a second algorithm which makes low device count implementations possible.

9. 发明申请

WO2021133371A1 DIGITAL-TO-ANALOG CONVERTER, DATA PROCESSING SYSTEM, BASE STATION AND MOBILE DEVICE 审中-公开
公开(公告)号：WO2021133371A1
公开(公告)日：2021-07-01
申请号：PCT/US2019/068225
申请日：2019-12-23
申请人： INTEL CORPORATION
发明人： SHIN, Hundo , GRUBER, Daniel , CLARA, Martin , WANG, Yu-Shan , AZADET, Kameran
IPC分类号： H03M1/72 , H03M1/66
摘要： A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.

10. 发明申请

WO2019237115A1 CLOCKLESS TIME-TO-DIGITAL CONVERTER 审中-公开
公开(公告)号：WO2019237115A1
公开(公告)日：2019-12-12
申请号：PCT/US2019/036372
申请日：2019-06-10
申请人： COHEN, Seth, D.
发明人： COHEN, Seth, D.
IPC分类号： H03M1/12 , H03M1/14 , H03M1/72
摘要： Technologies are provided for time-to-digital conversion without reliance on a clocking signal. Some embodiments of the technologies include a clockless TDC apparatus that can map continuous pulse-widths to binary bits represented via an iterative chaotic map (e.g., tent map, Bernoulli shift map, or similar). The clockless TDC apparatus can convert separated pulses to a single asynchronous digital pulse that turns on when a sensor detects a first pulse and turns off when the sensor detects a second pulse. The asynchronous digital pulse can be iteratively stretched and folded in time according to the chaotic map. The clockless TDC can generate a binary sequence that represents symbolic dynamics of the chaotic map. The process can be implemented by using an iterative time delay component until a precision of the binary output is either satisfied or overwhelmed by noise or other structural fluctuations of the TDC apparatus.

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