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1. 发明申请

WO2015030834A1 INCREASED REFRESH INTERVAL AND ENERGY EFFICIENCY IN A DRAM 审中-公开
标题翻译：在DRAM中增加了刷新间隔和能源效率
公开(公告)号：WO2015030834A1
公开(公告)日：2015-03-05
申请号：PCT/US2013/057757
申请日：2013-09-01
申请人： EMPIRE TECHNOLOGY DEVELOPMENT LLC
发明人： SOLIHIN, Yan
IPC分类号： G11C11/406 , G11C29/24 , G11C29/54
CPC分类号： G06F11/004 , G11C7/1072 , G11C11/40 , G11C11/406 , G11C11/40618 , G11C11/4074 , G11C29/023 , G11C29/028 , G11C29/44 , G11C29/50016 , G11C29/783 , G11C2211/4061
摘要： Techniques described herein generally include methods and systems related to designing and operating a DRAM device that has significantly reduced refresh energy use. A method for designing a DRAM optimizes or otherwise improves the DRAM for energy efficiency based on a measured or predicted failure probability of memory cells in the DRAM. The DRAM may be configured to operate at an increased refresh interval, thereby reducing DRAM refresh energy but causing a predictable portion of the memory cells in the DRAM to leak electrical energy too quickly to retain data. The DRAM is further configured with a selected a number of spare memory cells for replacing the "leaky" memory cells, so that operation of the DRAM at the increased refresh interval may result in little or no reduction in capacity of the DRAM.
摘要翻译：本文描述的技术通常包括与设计和操作具有显着降低的刷新能量使用的DRAM设备相关的方法和系统。基于DRAM中的存储器单元的测量或预测的故障概率，用于设计DRAM的方法优化或以其他方式改进用于能量效率的DRAM。 DRAM可以被配置为以增加的刷新间隔进行操作，从而减少DRAM刷新能量，但是使DRAM中的存储器单元的可预测部分太快地泄漏电能以保留数据。 DRAM进一步配置有选择的多个备用存储器单元以替换“泄漏”存储单元，使得在增加的刷新间隔的DRAM的操作可能导致DRAM的容量很少或不降低。

2. 发明申请

WO2005072305A2 EFFICIENT MODELING OF EMBEDDED MEMORIES IN BOUNDED MEMORY CHECKING 审中-公开
标题翻译：嵌入式记忆的有效建模在边界记忆检查中的应用
公开(公告)号：WO2005072305A2
公开(公告)日：2005-08-11
申请号：PCT/US2005/002176
申请日：2005-01-20
申请人： NEC LABORATORIES AMERICA, INC.
发明人： GANAI, Malay , GUPTA, Aarti , ASHAR, Pranav, N.
IPC分类号： G06F17/50 , G11C29/54
CPC分类号： G11C29/54 , G06F17/504 , G11C2029/0401
摘要： A computer-implemented method for augmenting SAT-based BMC to handle embedded memory designs without explicitly modeling memory bits. As is known, verifying designs having large embedded memories is typically handled by abstracting out (over-approximating) the memories. Such abstraction is not useful for finding real bugs. SAT-based BMC, as of now, is incapable of handling designs with explicit memory modeling due to enormously increased search space complexity. Advantageously, our method does not require analyzing the designs and also guarantees not to generate false negatives.
摘要翻译：一种用于增加基于SAT的BMC来处理嵌入式存储器设计而不明确建模存储器位的计算机实现的方法。众所周知，验证具有大嵌入存储器的设计通常通过抽象出（过近似）存储器来处理。这样的抽象对于找到真实的错误是没有用的。目前，基于SAT的BMC由于搜索空间复杂度的大幅增加，无法处理具有显式内存建模的设计。有利的是，我们的方法不需要分析设计，也不保证不产生假阴性。

3. 发明申请

WO2021128169A1 芯片设计方法、芯片设计设备和存储介质审中-公开
公开(公告)号：WO2021128169A1
公开(公告)日：2021-07-01
申请号：PCT/CN2019/128730
申请日：2019-12-26
申请人：深圳市大疆创新科技有限公司
发明人：邵帅 , 欧宇 , 范傲
IPC分类号： G11C29/54 , G06F2119/02 , G06F2119/06 , G06F30/20 , G06F30/327 , G06F30/337 , G06F30/394
摘要：一种芯片设计方法、芯片设计设备和存储介质。芯片设计方法包括：获取与芯片设计代码中单元模块相对应的翻转率配置信息（S101）；确定与单元模块相对应的布局布线网表和标准寄生交换格式文件（S102）；根据翻转率配置信息、布局布线网表和标准寄生交换格式文件，确定与芯片设计代码中的单元模块相对应的芯片功耗，以用于芯片设计（S103）。所述方法提高了芯片功耗的评估操作的质量和效率。

4. 发明申请

WO2011116056A3 MODELING OF CELL DELAY CHANGE FOR ELECTRONIC DESIGN AUTOMATION 审中-公开
标题翻译：电子设计自动化中细胞延迟变化的建模
公开(公告)号：WO2011116056A3
公开(公告)日：2011-11-24
申请号：PCT/US2011028613
申请日：2011-03-16
申请人： SYNOPSYS INC , TANG QIAN-YING , CHEN QIANG , TIRUMALA SRIDHAR
发明人： TANG QIAN-YING , CHEN QIANG , TIRUMALA SRIDHAR
IPC分类号： G06F19/00 , G06F9/44 , G06F17/50 , G11C29/54
CPC分类号： G06F17/5009 , G06F17/5022 , G06F17/5036 , G06F2217/84
摘要： An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short- circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.
摘要翻译：用于修改单元特征（例如，栅极长度）的集成电路设计优化程序模拟由于修改而引起的延迟变化。在延迟变化计算中，针对修改的单元确定单元切换行为中的事件的特性，例如输出短路电压VSC，其中所确定的特性中的变化与由于修改。接下来，根据所确定的事件特征确定修改小区的延迟值。该过程可以在布置和布线之后应用。使用延迟变化模型来描述时序受限的泄漏功率减小。

5. 发明申请

WO2005072305A3 EFFICIENT MODELING OF EMBEDDED MEMORIES IN BOUNDED MEMORY CHECKING 审中-公开
标题翻译：嵌入式记忆的有效建模在边界记忆检查中的应用
公开(公告)号：WO2005072305A3
公开(公告)日：2007-01-04
申请号：PCT/US2005002176
申请日：2005-01-20
申请人： NEC LAB AMERICA INC
发明人： GANAI MALAY , GUPTA AARTI , ASHAR PRANAV N
IPC分类号： G06F17/50 , G11C29/54
CPC分类号： G11C29/54 , G06F17/504 , G11C2029/0401
摘要： A computer-implemented method for augmenting SAT-based BMC to handle embedded memory designs without explicitly modeling memory bits. As is known, verifying designs having large embedded memories is typically handled by abstracting out (over-approximating) the memories. Such abstraction is not useful for finding real bugs. SAT-based BMC, as of now, is incapable of handling designs with explicit memory modeling due to enormously increased search space complexity. Advantageously, our method does not require analyzing the designs and also guarantees not to generate false negatives.
摘要翻译：一种用于增加基于SAT的BMC来处理嵌入式存储器设计而不明确建模存储器位的计算机实现的方法。众所周知，验证具有大嵌入存储器的设计通常通过抽象出（过近似）存储器来处理。这样的抽象对于找到真正的错误是没有用的。目前，基于SAT的BMC由于搜索空间复杂度的大幅增加，无法处理具有显式内存建模的设计。有利地，我们的方法不需要分析设计，并且也保证不产生假阴性。

6. 发明申请

WO2021163136A1 DESIGN OF DYNAMIC RANDOM-ACCESS MEMORY PASS TRANSISTORS WITH STATISTICAL VARIATIONS IN LEAKAGE CURRENTS 审中-公开
公开(公告)号：WO2021163136A1
公开(公告)日：2021-08-19
申请号：PCT/US2021/017385
申请日：2021-02-10
申请人： SYNOPSYS, INC.
发明人： AMOROSO, Salvatore Maria , ASENOV, Plamen A. , LEE, Jaehyun , BROWN, Andrew R. , ALDEGUNDE RODRIGUEZ, Manuel , CHENG, Binjie , PENDER, Andrew John , REID, David T.
IPC分类号： G11C29/04 , G11C11/402 , G11C29/54 , G06F30/367 , G11C11/407 , G11C29/02 , H01L27/108
摘要： The design of Dynamic Random Access Memory (DRAM) pass transistors is provided via generating a first plurality of transistor leakage currents by simulating different dopant configurations in a transistor; generating a second plurality of transistor leakage currents by simulating, for each dopant configuration of the different dopant configurations, a single trap insertion in the transistor; fitting the first and second pluralities of transistor leakage currents with first and second leakage current distributions; combining the first and second leakage current distributions to produce a third leakage current distribution; generating a third plurality of statistically generated leakage currents for a specified trap density for the transistor based on the first leakage current distribution, on the second leakage current distribution and on a specified trap density; and modeling and evaluating a DRAM cell including the transistor based on the third plurality of statistically generated leakage currents.

7. 发明申请

WO2021134093A1 MEMORY ARRAY STRUCTURES AND METHODS FOR DETERMINATION OF RESISTIVE CHARACTERISTICS OF ACCESS LINES 审中-公开
公开(公告)号：WO2021134093A1
公开(公告)日：2021-07-01
申请号：PCT/US2020/070869
申请日：2020-12-07
申请人： MICRON TECHNOLOGY, INC.
发明人： XU, Dan , XU, Jun , YU, Erwin E. , TESSARIOL, Paolo , IWASAKI, Tomoka Ogura
IPC分类号： G11C8/14 , G11C29/02 , G11C5/02 , G11C5/06 , G11C16/04 , G11C16/08 , G11C29/12 , G11C29/24 , G11C29/44 , H01L27/115 , G11C29/54 , G11C13/003 , G11C13/0038 , G11C16/0483 , G11C2029/1202 , G11C2029/4402 , G11C29/025 , G11C29/028 , G11C5/025 , G11C5/063 , G11C5/066
摘要： Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.

8. 发明申请

WO2017014894A1 NON-INTRUSIVE PROBE FOR DOUBLE DATA RATE INTERFACE 审中-公开
标题翻译：用于双重数据速率接口的非入侵探测器
公开(公告)号：WO2017014894A1
公开(公告)日：2017-01-26
申请号：PCT/US2016/038581
申请日：2016-06-21
申请人： QUALCOMM INCORPORATED
发明人： DING, Chong , WHITE, Douglas Bruce , DRAUGHN, Roy
IPC分类号： G11C29/02 , G11C29/56 , G11C29/54
CPC分类号： G06F11/263 , G06F11/221 , G11C29/021 , G11C29/025 , G11C29/54 , G11C29/56012 , G11C29/56016 , G11C2029/5602
摘要： A method and apparatus using a non-intrusive probe for testing double data rate interfaces is provided. The method begins with the generation of at least one component parameter model, which is then cascaded to form a full system parameter model of the double data rate interface being tested. Transfer functions are generated using the full system parameter model. A target transfer function is calculated between the test equipment and a decision point. The calculated target transfer function is applied and testing is completed. The apparatus includes a device to be tested, mounted on a circuit board. A probe card is attached to the backside of the circuit board and is in communication with a high-speed connector. At least one connector in communication with the high-speed connector and at least one small footprint RF connector on an accessible side of the circuit board are also part of the non-intrusive probing apparatus.
摘要翻译：提供了一种使用非入侵探测器测试双数据速率接口的方法和装置。该方法开始于生成至少一个组件参数模型，然后将其级联以形成正在测试的双数据速率接口的完整系统参数模型。使用完整的系统参数模型生成传输函数。在测试设备和决策点之间计算目标传递函数。计算出的目标传递函数被应用并且测试完成。该装置包括安装在电路板上的待测试装置。探针卡连接到电路板的背面并与高速连接器通信。至少一个与高速连接器连接的连接器和电路板可触及侧上的至少一个小尺寸RF连接器也是非侵入式探测装置的一部分。

9. 发明申请

WO2020030590A1 A DIGITAL CIRCUIT TESTING AND ANALYSIS MODULE, SYSTEM AND METHOD THEREOF 审中-公开
公开(公告)号：WO2020030590A1
公开(公告)日：2020-02-13
申请号：PCT/EP2019/071023
申请日：2019-08-05
申请人： NUMASCALE AS
发明人： PALFER-SOLLIER, Thibaut , RUSTAD, Einar , PERSVOLD, Steffen
IPC分类号： G11C29/38 , G11C29/54 , G06F11/36
摘要： The present invention is related to a digital circuit testing and analysis module system comprising a memory (22). The memory (22) is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.

10. 发明申请

WO2019140361A1 LOW-OBSERVABILITY MATRIX COMPLETION 审中-公开
公开(公告)号：WO2019140361A1
公开(公告)日：2019-07-18
申请号：PCT/US2019/013458
申请日：2019-01-14
申请人： ALLIANCE FOR SUSTAINABLE ENERGY, LLC
发明人： BERNSTEIN, Andrey , ZHANG, Yingchen , SCHMITT, Andreas Joachim
IPC分类号： G06F17/40 , G06F17/50 , G11C29/54
摘要： An example device includes at least one processor configured to receive electrical parameter values corresponding to at least one first location within a power network. The at least one processor is further configured to determine, using matrix completion and based on the at least one electrical parameter value, an estimated value of at least one unknown electrical parameter. The at least one unknown electrical parameter corresponds to a second location within the power network. The at least one processor is also configured to cause at least one device within the power network to modify operation based on the estimated value of the at least one unknown electrical parameter.

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