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1. 发明申请

WO0011607A8 DEFERRED SHADING GRAPHICS PIPELINE PROCESSOR 审中-公开
标题翻译：缩减图形管道处理器
公开(公告)号：WO0011607A8
公开(公告)日：2000-06-08
申请号：PCT/US9919191
申请日：1999-08-20
申请人： APPLE COMPUTER
发明人： DULUK JEROME F JR , HESSEL RICHARD E , ARNOLD VAUGHN T , BENKUAL JACK , BRATT JOSEPH P , CUAN GEORGE , DODGEN STEVEN L , FANG EMERSON S , GONG ZHAOYU G , HO THOMAS Y , HSU HENGWEI , LI SIDONG , NG SAM , PAPAKIPOS MATTHEW N , REDGRAVE JASON R , TRIVEDI SUSHMA S , TUCK NATHAN D
IPC分类号： G06T1/60 , G06T11/00 , G06T15/00 , G06T15/04 , G06T15/20 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87 , G06T1/20
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： Three-dimensional computer graphics system and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is a Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch and decode (2000), a geometry unit (3000), a mode extraction (4000) and polygon memory (5000), a sort unit (6000) and sort memory (7000), a setup unit (8000), a cull unit (9000), a mode injection (10000), a fragment unit (11000), a texture (12000) and texture memory (13000), a phong shading (14000), a pixel unit (15000), a backend unit (16000) coupled to a frame buffer (17000). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.
摘要翻译：三维计算机图形系统和方法，更具体地涉及三维图形处理器的结构和方法，并具有其他增强的图形处理特征。在一个实施例中，图形处理器是包括AGP接口，命令提取和解码（2000），几何单元（3000），模式提取（4000）和多边形存储器（5000）的延迟着色图形处理器（DSGP）分类单元（6000）和分类存储器（7000），设置单元（8000），剔除单元（9000），模式注入（10000），片段单元（11000），纹理（12000）和纹理存储器），阴影（14000），像素单元（15000），耦合到帧缓冲器（17000）的后端单元（16000）。其他实施例不需要包括所有这些功能单元，并且这些单元的结构和方法适用于其他计算过程和系统以及延迟和非延迟着色图形处理器。

2. 发明申请

WO0011562B1 APPARATUS AND METHOD FOR PERFORMING SETUP OPERATIONS IN A 3-D GRAPHICS PIPELINE USING UNIFIED PRIMITIVE DESCRIPTORS 审中-公开
标题翻译：使用统一原始描述符在三维图形管道中执行设置操作的装置和方法
公开(公告)号：WO0011562B1
公开(公告)日：2000-05-04
申请号：PCT/US9919240
申请日：1999-08-20
申请人： APPLE COMPUTER
发明人： DULUK JEROME F JR , HESSEL RICHARD E , ARNOLD VAUGHN T , BENKUAL JACK , CUAN GEORGE , DODGEN STEVEN L , FANG EMERSON S , HSU HENGWEI , TRIVEDI SUSHMA S
IPC分类号： G06T1/60 , G06T11/00 , G06T15/00 , G06T15/04 , G06T15/20 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87 , G06F15/00
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： The present invention provides a post tile sorting setup in a tiled graphics pipeline architecture (200). In particular, the present invention determines a set of clipping points that identify intersections of a primitive with a tile. The mid-pipeline setup (215) unit is adapted to compute a minimum depth value for that part of the primitive intersecting the tile. The mid-pipeline setup unit can be adapted to process primitives with x-coordinates that are screen based and y-coordinates that are tile based. Additionally, to the mid-pipeline setup unit is adapted to represent both line segments and triangles as quadrilaterals, wherein not all of a quadrilateral's vertices are required to describe a triangle.
摘要翻译：本发明提供了平铺图形流水线体系结构（200）中的后平铺分类设置。特别地，本发明确定识别基元与瓦片的交集的一组剪切点。中间管线设置（215）单元适于为与图块相交的图元部分计算最小深度值。中间管线设置单元可适用于处理基于x坐标的图元，这些坐标是基于图块的基于屏幕的坐标和y坐标。另外，中间管线设置单元适于将线段和三角形都表示为四边形，其中不是所有的四边形顶点都需要描述三角形。

3. 发明申请

WO00011603A2 GRAPHICS PROCESSOR WITH PIPELINE STATE STORAGE AND RETRIEVAL 审中-公开
标题翻译：图形处理器与管状态存储和检索
公开(公告)号：WO00011603A2
公开(公告)日：2000-03-02
申请号：PCT/US1999/019200
申请日：1999-08-20
IPC分类号： G06T1/60 , G06T11/00 , G06T15/00 , G06T15/04 , G06T15/20 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87 , G06T
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.
摘要翻译：延迟图形流水线处理器，包括与多边形单元相关联的模式提取单元和多边形存储器。模式提取单元从几何单元接收数据流，并将数据流分离成顶点数据，并将非顶点数据发送到多边形存储器进行存储。模式注入单元从多边形存储器接收输入并将模式信息传送到一个或多个其他处理单元。模式注入单元保持识别已经缓存的信息的状态信息，并且不发送已经被缓存的信息，从而减少通信带宽。

4. 发明申请

WO0011602A9 METHOD AND APPARATUS FOR GENERATING TEXTURE 审中-公开
标题翻译：用于生成纹理的方法和装置
公开(公告)号：WO0011602A9
公开(公告)日：2000-09-08
申请号：PCT/US9919192
申请日：1999-08-20
申请人： APPLE COMPUTER
发明人： DULUK JEROME F JR , HESSEL RICHARD E , GRASS JOSEPH P , RASHID ABBAS , HONG BO , MAMMEN ABRAHAM
IPC分类号： G06T1/60 , G06T11/00 , G06T15/00 , G06T15/04 , G06T15/20 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87 , G06T
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.
摘要翻译：一种延迟图形流水线处理器，包括与纹理单元相关联的纹理单元和纹理存储器。纹理单元将存储在纹理存储器中的纹理映射应用于像素片段。纹理是MIP映射的，并且包括不同细节级别的一系列纹理贴图，每个贴图表示在距离眼点的给定距离处的纹理的外观。纹理单元从纹理图执行三线性插值，以产生近似正确的细节水平的给定像素片段的纹理值。纹理存储器以减少存储器访问冲突的方式存储和访问纹理数据，从而提高所述纹理单元的吞吐量。

5. 发明申请

WO00011562A1 APPARATUS AND METHOD FOR PERFORMING SETUP OPERATIONS IN A 3-D GRAPHICS PIPELINE USING UNIFIED PRIMITIVE DESCRIPTORS 审中-公开
标题翻译：使用统一的初步描述符在三维图形管道中执行设置操作的装置和方法
公开(公告)号：WO00011562A1
公开(公告)日：2000-03-02
申请号：PCT/US1999/019240
申请日：1999-08-20
IPC分类号： G06T1/60 , G06T11/00 , G06T15/00 , G06T15/04 , G06T15/20 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87 , G06F15/00
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： The present invention provides a post tile sorting setup in a tiled graphics pipeline architecture (200). In particular, the present invention determines a set of clipping points that identify intersections of a primitive with a tile. The mid-pipeline setup (215) unit is adapted to compute a minimum depth value for that part of the primitive intersecting the tile. The mid-pipeline setup unit can be adapted to process primitives with x-coordinates that are screen based and y-coordinates that are tile based. Additionally, to the mid-pipeline setup unit is adapted to represent both line segments and triangles as quadrilaterals, wherein not all of a quadrilateral's vertices are required to describe a triangle.
摘要翻译：本发明提供了一种平铺图形流水线架构（200）中的贴片排列设置。特别地，本发明确定了识别原始图像与瓦片的交叉点的一组剪切点。中间管道设置（215）单元适于计算与瓦片相交的原始部分的最小深度值。中间流水线设置单元可以适用于处理基于屏幕的x坐标的基元和基于瓦片的y坐标。另外，中间流水线设置单元适于将线段和三角形表示为四边形，其中不需要全部四边形的顶点来描述三角形。

6. 发明申请

WO0011603A9 GRAPHICS PROCESSOR WITH PIPELINE STATE STORAGE AND RETRIEVAL 审中-公开
标题翻译：图形处理器与管道状态存储和检索
公开(公告)号：WO0011603A9
公开(公告)日：2000-09-08
申请号：PCT/US9919200
申请日：1999-08-20
申请人： APPLE COMPUTER
发明人： DULUK JEROME F JR , BENKUAL JACK , GO SHUN WAI , TRAVEDI SUSHMA , HESSEL RICHARD E , BRATT JOSEPH P
IPC分类号： G06T1/60 , G06T11/00 , G06T15/00 , G06T15/04 , G06T15/20 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87 , G06T
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.
摘要翻译：一个延迟图形流水线处理器，由一个模式提取单元和一个与多边形单元相关的多边形存储器组成。模式提取单元接收来自几何单元的数据流并将数据流分离成顶点数据以及发送到多边形存储器以供存储的非顶点数据。模式注入单元接收来自多边形存储器的输入并将模式信息传送给一个或多个其他处理单元。模式注入单元维护标识已经被高速缓存的信息的状态信息并且不发送已经高速缓存的信息，由此减少通信带宽。

7. 发明申请

WO0011607B1 DEFERRED SHADING GRAPHICS PIPELINE PROCESSOR 审中-公开
标题翻译：缩减图形管道处理器
公开(公告)号：WO0011607B1
公开(公告)日：2000-05-04
申请号：PCT/US9919191
申请日：1999-08-20
申请人： RAYCER INC
发明人： DULUK JEROME F JR , HESSEL RICHARD E , ARNOLD VAUGHN T , BENKUAL JACK , BRATT JOSEPH P , CUAN GEORGE , DODGEN STEVEN L , FANG EMERSON S , GONG ZHAOYU G , HO THOMAS Y , HSU HENGWEI , LI SIDONG , NG SAM , PAPAKIPOS MATTHEW N , REDGRAVE JASON R , TRIVEDI SUSHMA S , TUCK NATHAN D
IPC分类号： G06T1/60 , G06T11/00 , G06T15/00 , G06T15/04 , G06T15/20 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87 , G06T1/20
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch and decode (2000), a geometry unit (3000), a mode extraction (4000) and polygon memory (5000), a sort unit (6000) and sort memory (7000), a set up unit (8000), a cull unit (9000), a mode injection (10000), a fragment unit (11000), a texture (12000) and texture memory (13000), a phong shading (14000), a pixel unit (15000), a backend unit (16000) coupled to a frame buffer (17000).
摘要翻译：包括AGP接口，命令提取和解码（2000），几何单元（3000），模式提取（4000）和多边形存储器（5000），分类单元（6000）和分类的延迟着色图形处理器（DSGP）存储器（7000），设置单元（8000），剔除单元（9000），模式注入（10000），片段单元（11000），纹理（12000）和纹理存储器（13000） 14000），像素单元（15000），耦合到帧缓冲器（17000）的后端单元（16000）。

8. 发明申请

WO00011607A1 DEFERRED SHADING GRAPHICS PIPELINE PROCESSOR 审中-公开
标题翻译：处理器图形阴影管道报告
公开(公告)号：WO00011607A1
公开(公告)日：2000-03-02
申请号：PCT/US1999/019191
申请日：1999-08-20
IPC分类号： G06T1/60 , G06T11/00 , G06T15/00 , G06T15/04 , G06T15/20 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87 , G06T1/20
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： Three-dimensional computer graphics system and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is a Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch and decode (2000), a geometry unit (3000), a mode extraction (4000) and polygon memory (5000), a sort unit (6000) and sort memory (7000), a setup unit (8000), a cull unit (9000), a mode injection (10000), a fragment unit (11000), a texture (12000) and texture memory (13000), a phong shading (14000), a pixel unit (15000), a backend unit (16000) coupled to a frame buffer (17000). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.
摘要翻译：延迟阴影图形处理器（DGSE）包括加速图形端口（AGA）接口，恢复和解码控制（2000），几何单元（3000），模式提取单元（4000）和存储器（5000），分类单元（6000）和分类存储器（7000），基本单元（8000），废弃单元（9000），模式注入单元（10000），分割单元（11,000），纹理单元（12,000）和纹理存储器（13,000），电话阴影（14,000），像素单元（15,000），主系统单元 16,000）耦合到图形内存（17,000）。

9. 发明申请

WO00010372A2 SYSTEM, APPARATUS AND METHOD FOR SPATIALLY SORTING IMAGE DATA IN A THREE-DIMENSIONAL GRAPHICS PIPELINE 审中-公开
标题翻译：用于在三维图形管道中空间分类图像数据的系统，装置和方法
公开(公告)号：WO00010372A2
公开(公告)日：2000-03-02
申请号：PCT/US1999/019263
申请日：1999-08-20
IPC分类号： G06T1/60 , G06T11/00 , G06T15/00 , G06T15/04 , G06T15/20 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： The present invention is a mid-pipeline sorting unit that sorts image data mid-pipeline in a tiled 3-D graphics pipeline architecture. The image data includes vertices of geometric primitives. The mid-pipeline sorting determines whether a geometric primitive intersects a region of a 2-D window. The 2-D window having been divided into multiple such regions. Upon determining which region of the 2-D window that the geometric primitive intersects, the mid-pipeline sorting unit stores the vertices that define the geometric primitive into a memory in a manner that associates each of the geometric primitive's vertices with the region that was intersected. After the image data is sorted into the memory, the mid pipeline sorting unit sends the sorted image data to the subsequent stage on a region by region basis. Yet another embodiment of the present invention provides a guaranteed conservative memory estimate to the mid-pipeline sorting stage of whether there is enough free memory for the mid pipeline sorting unit to sort and store the image data. Yet another embodiment of the present invention sends image data from a memory to a next stage in a graphics pipeline in a spatially staggered sequence.
摘要翻译：本发明是一种中间流水线分拣单元，其以平铺的3-D图形流水线架构中间管线分类图像数据。图像数据包括几何图元的顶点。中间流水线排序确定几何图元是否与2-D窗口的区域相交。 2-D窗口已分为多个这样的区域。在确定几何图元相交的2-D窗口的哪个区域时，中间流水线分类单元以将每个几何图元的顶点与相交的区域相关联的方式将定义几何基元的顶点存储到存储器中。在将图像数据分类到存储器中之后，中间流水线分拣单元在逐个区域的基础上将排序的图像数据发送到后续的阶段。本发明的另一个实施例提供了对中间流水线分类阶段的保证的保守的存储器估计是否存在足够的空闲存储器，用于中间管道分类单元对图像数据进行分类和存储。本发明的另一个实施例将图像数据从空间交错序列的图形管线中的存储器发送到下一级。

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