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1. 发明申请

WO2004066499A1 半導体集積回路审中-公开
标题翻译：半导体集成电路
公开(公告)号：WO2004066499A1
公开(公告)日：2004-08-05
申请号：PCT/JP2003/000403
申请日：2003-01-20
申请人：株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ , 能登隆行 , 佐藤点 , 山内裕之
发明人：能登隆行 , 佐藤点 , 山内裕之
IPC分类号： H03K19/00
CPC分类号： H04L25/0278 , H03K5/086 , H03K17/08142 , H03K17/164 , H03K17/167 , H03K19/0005 , H04L25/0292
摘要：　信号を取り込むための入力回路と、信号を出力するための出力回路とを含む半導体集積回路において、上記入力回路は、入力信号遷移時の入力インピーダンスが、入力信号遷移時以外の入力インピーダンスよりも小さくなるように設定され、上記出力回路は、信号遷移の後半での駆動力が遷移の前半での駆動力よりも低めに設定される。入力信号遷移時の入力インピーダンスが、入力信号遷移時以外の入力インピーダンスよりも小さくなるように設定することは、入力信号遷移時における反射波を低減する。また、信号遷移の後半での駆動力が遷移の前半での駆動力よりも低めに設定することは、信号遷移の後半での反射波の発生を抑える。これにより、インピーダンス整合のためのダンピング抵抗や終端抵抗などの外付け部品を不要とする。
摘要翻译：一种具有用于获取信号的输入电路和用于输出信号的输出电路的半导体集成电路。输入电路被设置为使得输入信号转换处的输入阻抗小于输入信号转换以外的输入阻抗。输出电路被设定为使得信号转变的后半部分的驱动力低于转换的前半部分的驱动力。由于输入信号转换时的输入阻抗设定为小于输入信号转换以外的输入阻抗，所以输入信号转换时的反射波减小。此外，由于信号转变的后半部分的驱动力被设定为低于转换的前半部分的驱动力，所以抑制了信号转变后半部分处的反射波的产生。这就消除了外部部件的需要，例如用于阻抗匹配的倾销电阻器和终端电阻器。

2. 发明申请

WO01020782A1 CIRCUIT ARRANGEMENT FOR CONTROLLING A LOAD 审中-公开
标题翻译：电路用于控制负载
公开(公告)号：WO01020782A1
公开(公告)日：2001-03-22
申请号：PCT/EP2000/009050
申请日：2000-09-15
IPC分类号： H03K17/0412 , H03K17/16 , H03K19/003 , H03K17/042
CPC分类号： H03K17/167 , H03K17/04123 , H03K19/00361
摘要： The invention relates to a circuit arrangement alternating connection of a load to a high and low supply potential according to a control signal supplied to an input. The inventive circuit arrangement has a first push-pull output stage consisting of a first and second semi-conductor switch. Said output stage is switched between a first and a second supply potential connection. A load is connected to a connection point of a first and second semi-conductor switch. A second push-pull stage consisting of a third and a fourth semi-conductor switch is also provided,. Said switches are mounted between a first and a second supply potential connection, whereby a semi-conducting switch of the second of the second push-pull output stage only conducts when a semi-conductor switch of the first push-pull output stage is blocked. A power-semi-conductor switch is intended to act as a load. Said semiconductor switch which forms the base element of a synchronized electrical supply in conjunction with a transformer coil.
摘要翻译：它提出了一种电路装置，用于改变连接负载具有高的，并且根据驱动信号到一个输入的低电源电位。该电路装置包括由第一和第二半导体开关的第一推挽输出级。这是一个第一和第二电源电势连接之间互连。负载被连接到所述第一和所述第二半导体开关的连接点。此外，提供由第三和第四半导体开关的第二推挽输出级，其第一和第二Versorgunspotentialanschluss之间互连，其中所述第二推挽输出级的半导体开关，只有当第一推挽输出级的半导体开关被关断导通。作为负载，特别是功率半导体开关被提供，其与变压器的线圈形成一个开关模式电源的基本要素结合。

3. 发明申请

WO00054409A1 CIRCUIT HAVING OUTPUT BUFFER WITH DYNAMIC IMPEDANCE 审中-公开
标题翻译：具有动态阻抗的输出缓冲器的电路
公开(公告)号：WO00054409A1
公开(公告)日：2000-09-14
申请号：PCT/EP2000/001337
申请日：2000-02-18
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K17/167 , H03K19/00361
摘要： A circuit has an output buffer that is switchable between at least a lower and a higher output impedance mode. The lower impedance mode is selected after logic transitions on the input and the higher impedance mode when a signal at the output enters a predetermined range around a nominal level required by the input. The circuit comprises a memory circuit (160) for blocking switch-back to the lower output impedance mode after the signal at the output has been in the predetermined range as long the output signal at the input does not change.
摘要翻译：电路具有可在至少较低和较高输出阻抗模式之间切换的输出缓冲器。当输入端的信号在输入所要求的标称电平附近进入预定范围时，在输入和较高阻抗模式下的逻辑转换之后选择较低阻抗模式。该电路包括用于在输出端的信号处于预定范围内，只要输入端的输出信号不改变，就阻止切换回较低输出阻抗模式的存储电路（160）。

4. 发明申请

WO1997004528A1 LOW NOISE TRI-STATE OUTPUT BUFFER 审中-公开
标题翻译：低噪声三态输出缓冲器
公开(公告)号：WO1997004528A1
公开(公告)日：1997-02-06
申请号：PCT/US1996010980
申请日：1996-06-26
申请人： KAPLINSKY, Cecil, H.
IPC分类号： H03K19/0948
CPC分类号： H03K19/00361 , H03K17/167 , H03K19/09429
摘要： A buffer circuit includes a pair of pull-up output transistors (11, 13) and a pair of pull-down output transistors (15, 17) driving an output line (19, 20). Each output transistor is driven by its own tristate input translator (23, 25, 27, 29), all connected to an input terminal (22) of the circuit. Two of the translators (25, 29) are tristated by control signals (51, 52) received as feedback from the output line to turn off one of the pull-up transistors (13) when the output voltage exceeds the high logic level transition voltage (2.2 V) and to turn off one of the pull-down transistors (17) when the output drops below the low logic level transition voltage (0.8 V). This not only prevents ground bounce or overshoot of the output, but also avoids larger current flow or power dissipation from pull-up and pull-down transistors being simultaneously partially on during a transition.
摘要翻译：缓冲电路包括一对上拉输出晶体管（11,13）和一对驱动输出线（19,20）的下拉输出晶体管（15,17）。每个输出晶体管由其自身的三态输入转换器（23,25,27,29）驱动，全部连接到电路的输入端（22）。当输出电压超过高逻辑电平转换电压时，两个转换器（25,29）由作为反馈从输出线接收的控制信号（51,52）进行三态转换，以截止上拉晶体管（13）中的一个（2.2V），并且当输出低于低逻辑电平转变电压（0.8V）时，关闭其中一个下拉晶体管（17）。这不仅可以防止输出的接地反弹或过冲，而且可以避免在转换期间上拉和下拉晶体管同时部分导通的较大电流或功耗。

5. 发明申请

WO2017199772A1 SLEW RATE CONTROL APPARATUS 审中-公开
标题翻译：旋转速率控制装置
公开(公告)号：WO2017199772A1
公开(公告)日：2017-11-23
申请号：PCT/JP2017/017286
申请日：2017-05-02
申请人： RICOH ELECTRONIC DEVICES CO., LTD.
发明人： UJIIE, Ryuichi
IPC分类号： H03K17/16 , G06F1/26
CPC分类号： H03K17/167 , G06F1/26 , G06F1/263 , H03K2217/0054 , H03K2217/0063
摘要： A slew rate control apparatus includes voltage detecting means, charging and discharging means, and control means. The voltage detecting means detects a first voltage and a second voltage on both ends of at least one switch. The charging and discharging means outputs a current for charging at least one of the both ends of the switch and for inputting a current for discharging the at least one end. The control means controls a slew rate by turning on the switch when the first voltage detected by the voltage detecting means has reached the second voltage, and outputs a current for charging at least one of two terminals on the both ends of the switch or discharging the at least one terminal according to a magnitude relationship between the first voltage and the second voltage when the first voltage does not reached the second voltage.
摘要翻译：转换速率控制装置包括电压检测装置，充电和放电装置以及控制装置。电压检测装置检测至少一个开关的两端的第一电压和第二电压。充电和放电装置输出用于对开关的两端中的至少一端进行充电的电流并输入用于对至少一端进行放电的电流。当电压检测装置检测到的第一电压已经达到第二电压时，控制装置通过接通开关来控制转换速率，并输出用于对开关两端的至少一个端子充电的电流，当所述第一电压未达到所述第二电压时，根据所述第一电压与所述第二电压之间的大小关系来确定至少一个端子。

6. 发明申请

WO00011787A1 OUTPUT DRIVING CIRCUIT 审中-公开
标题翻译：输出驱动电路
公开(公告)号：WO00011787A1
公开(公告)日：2000-03-02
申请号：PCT/DE1999/002389
申请日：1999-08-02
IPC分类号： H03K17/16 , H03K17/687 , H03K17/695 , H03K19/003 , H03K19/0175 , H04L25/02
CPC分类号： H03K17/167 , H03K19/00361
摘要： The invention relates to an output driving circuit of an integrated circuit comprising several pairs of driver circuits (1, 2, 3, 4) and driver control circuits (5, 6, 7, 8) as well as a control device (9). Each pair of driver control circuit and driver circuit (1, 5/2, 6/3, 7/4, 8) forms a driving stage. The driving stages are connected in series. Based on the input signal of the output driving circuit, said control device (9) switches the signal direction through the succession of driving stages in such a way that, at the time the output driver circuit is switched either on or off, said driving stages are switched in a time delayed manner, whereby current pulses on the feeding lines and disturbance voltages induced in inductive loads are reduced.
摘要翻译：本发明涉及一种具有多个成对的驱动电路的集成电路的一输出驱动器电路（1，2，3，4）和驱动器驱动器（5，6，7，8）和控制装置（9）。每对驱动器控制和驱动电路的（1，5/2，6/3，7/4，8）形成一个驱动器级。驱动级串联一前一后。控制器（9）通过串联根据输出驱动器电路的输入信号驱动器级的开关信号传播的方向，这样既打开延迟接通时和关断输出驱动器电路的，因此电流脉冲的供给线和噪声电压在电感性负载引起的驱动器级将减少。

7. 发明申请

WO1997009783A1 RESONANT DRIVER CIRCUIT WITH REDUCED POWER CONSUMPTION 审中-公开
标题翻译：具有降低功耗的谐振驱动电路
公开(公告)号：WO1997009783A1
公开(公告)日：1997-03-13
申请号：PCT/GB1996002199
申请日：1996-09-06
申请人： HARVEY, Geoffrey, Philip
IPC分类号： H03K17/687
CPC分类号： H03K17/167 , H03K17/6872 , H03K19/0019 , H03K2217/0036
摘要： A driver circuit (18) generates a circuit output signal (VDO) which is provided to an electrical conductor (12) that furnishes a conductor output signal (VBO) to a load (14). The circuit and conductor output signals make corresponding circuit and conductor output transitions approximately between a pair of output voltage levels (VSS and VDD) between which there is an intermediate voltage level (VHH). Inductance (LB) and capacitance (CB and CL) of the conductor and load produce resonance that enables the conductor output signal to largely complete each conductor output transition while the circuit output signal is being held at or close to the intermediate voltage level for a short period. The circuit output signal rapidly completes each circuit output transition after the intermediate-level holding period is over. By operating in this manner, energy is re-used in a resonant manner, thereby substantially reducing power consumption.
摘要翻译：驱动器电路（18）产生电路输出信号（VDO），该电路输出信号（VDO）提供给向导体（14）提供导体输出信号（VBO）的电导体（12）。电路和导体输出信号使相应的电路和导体输出大致在一对输出电压电平（VSS和VDD）之间转换，其间有一个中间电压电平（VHH）。导体和负载的电感（LB）和电容（CB和CL）产生谐振，使得导体输出信号能够大大完成每个导体输出跃迁，同时电路输出信号被保持在或接近中间电压电平为短路期。在中间电平保持期结束后，电路输出信号迅速完成每个电路输出转换。通过以这种方式操作，以共振的方式重新使用能量，从而显着降低功耗。

8. 发明申请

WO1994010622A1 LOAD PROGRAMMABLE OUTPUT BUFFER 审中-公开
标题翻译：负载可编程输出缓冲器
公开(公告)号：WO1994010622A1
公开(公告)日：1994-05-11
申请号：PCT/US1993009951
申请日：1993-10-19
申请人： XILINX, INC.
发明人： XILINX, INC. , PIERCE, Kerry, M. , CARPENTER, Roger, D.
IPC分类号： G05F03/02
CPC分类号： G05F1/565 , H03K17/166 , H03K17/167
摘要： The present invention reduces bounce in the power (VCC) or ground (VSS) supply voltages of an integrated circuit chip by gradually turning output drivers (407b) both on and off, so there is not a sharp discontinuity in current flow to an external device (PAD). Greatest current flow occurs at the middle of a transition period. The gradual turn-off at the end of a transition is achieved by feeding back voltage of the output signal (408) to a device (501) which controls the output driver (407b). As output voltage approaches its final value, the output driver (407b) gradually turns off, preventing a sharp transient in the power (VCC) or ground (VSS) voltage of the integrated circuit chip.
摘要翻译：本发明通过逐渐地转动输出驱动器（407b）的导通和截止来减少集成电路芯片的电源（VCC）或接地（VSS）电源电压的反弹，因此电流流向外部设备没有尖锐的不连续性（垫）。最大电流在过渡期的中间发生。通过将输出信号（408）的电压反馈到控制输出驱动器（407b）的装置（501）来实现转换结束时的逐渐关断。当输出电压接近其最终值时，输出驱动器（407b）逐渐关闭，防止集成电路芯片的功率（VCC）或接地（VSS）电压的急剧瞬变。

9. 发明申请

WO1991009466A1 AUTO-DELAY GAIN CIRCUIT 审中-公开
标题翻译：自动延迟增益电路
公开(公告)号：WO1991009466A1
公开(公告)日：1991-06-27
申请号：PCT/EP1990001813
申请日：1990-10-23
申请人： VLSI TECHNOLOGY INC.
发明人： VLSI TECHNOLOGY INC. , HAQ, Ejaz, Ul
IPC分类号： H03K17/16
CPC分类号： H03K17/167
摘要： A multi-stage output buffer provides for inactivation and then delayed reactivation of a second gain stage (106) after a data transition. The delay imposed is a function of the output voltage, which is fed back through a threshold detector (110). A transition detector (112) is coupled to data inputs so that it can inactivate the second gain stage upon a data transition; the transition detector is coupled to the threshold detector so that it can activate the second gain stage once the output voltage crosses a predetermined threshold voltage. This configuration imposes relatively long delays on second gain stage activation when large loads are applied to keep switching transients to tolerable levels. When lesser loads are applied, a shorter delay permits more rapid throughput.

10. 发明申请

WO2014164316A1 INDUCTIVE LOAD DRIVER SLEW RATE CONTROLLER 审中-公开
标题翻译：电感负载驱动器低速控制器
公开(公告)号：WO2014164316A1
公开(公告)日：2014-10-09
申请号：PCT/US2014/021851
申请日：2014-03-07
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： DE GEETER, Bart , FURRER, Nicolas
IPC分类号： H03K17/16
CPC分类号： H03K5/04 , H03K17/166 , H03K17/167 , H03K17/6871 , H03K2217/0063 , H03K2217/0072
摘要： A circuit and method for digital controlling the slew rate of load voltage are provided. The circuit is comprised of a digital slew- rate control unit (504, 510) that utilizes a feedback signal (508) to generate control signals (in 501 and 502) where the feedback signal indicates the observed rate of voltage change on the load (505). The circuit is further comprised of a load driver circuit (503, 509) that is operated by the control signals and provides a slew-rate controlled output voltage used to operate a load switch (506, 507), where the load switch provides power to the load. The circuit is configured to operate the load switch using a slew-rate controlling driver, depending on the state of the load switch transition, and a non-controlling driver.
摘要翻译：提供了用于数字控制负载电压的转换速率的电路和方法。该电路由数字转换速率控制单元（504,510）组成，该数字转换速率控制单元利用反馈信号（508）产生控制信号（在501和502中），其中反馈信号指示观察到的负载上电压变化的速率（ 505）。电路还包括由控制信号操作的负载驱动器电路（503,509），并提供用于操作负载开关（506,507a）的压摆率控制的输出电压，其中负载开关向负载。电路被配置为使用压摆率控制驱动器来操作负载开关，这取决于负载开关转换的状态和非控制驱动器。

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